公开(公告)号：DE112016003974T5

公开(公告)日：2018-06-14

申请号：DE112016003974

申请日：2016-07-28

Applicant: INTEL CORP

Inventor： WU KEQUING ,  CHOW KINGSUM ,  FENG YING ,  BAN KHUN

IPC: G06F9/50

Abstract: Im Allgemeinen stellt diese Offenbarung Systeme, Vorrichtungen, Verfahren und computerlesbare Medien zum dynamischen Abstimmen von Multiprozessor- und Multikern-Rechnersystemen bereit, um die Anwendungsleistung und Skalierbarkeit zu verbessern. Ein System kann eine Anzahl von Prozessoreinheiten (CPUs) und eine Profilierungsschaltungsanordnung umfassen, die konfiguriert ist, das Vorliegen eines Skalierbarkeitsproblems zu detektieren, das der Ausführung einer Anwendung auf CPUs zugeordnet ist, und zu bestimmen, ob das Skalierbarkeitsproblem auf einen Zugriffskonflikt oder eine Ressourcenbeschränkung zurückzuführen ist. Das System kann auch eine Planungsschaltungsanordnung umfassen, die konfiguriert ist, die Anwendung an einen Teilsatz der Gesamtanzahl von CPUs anzubinden, falls das Skalierbarkeitsproblem auf einen Zugriffskonflikt zurückzuführen ist.

公开(公告)号：BR9813650A

公开(公告)日：2000-10-03

申请号：BR9813650

申请日：1998-12-11

Applicant: INTEL CORP

Inventor： AKKARY HAITHAM ,  CHOW KINGSUM

IPC: G06F9/38 ,  G06F9/46 ,  G06F9/30 ,  G06F9/40

Abstract: In one embodiment, a processor includes thread management logic including a thread predictor having state machines to indicate whether thread creation opportunities should be taken or not taken. The processor includes a predictor training mechanism to receive retired instructions and to identify potential threads from the retired instructions and to determine whether a potential thread of interest meets a test of thread goodness, and if the test is met, one of the state machines that is associated with the potential thread of interest is updated in a take direction, and if the test is not met, the state machine is updated in a not take direction. The thread management logic may control creation of an actual thread and may further include reset logic to control whether the actual thread is reset and wherein if the actual thread is reset, one of the state machines associated with the actual thread is updated in a not take direction. The final retirement logic may control whether the actual thread is retired, and wherein if the actual thread is retired, the state machine associated with the actual thread is updated in a take direction. The circuitry may be used in connection with a multi-threading processor that detects speculation errors involving thread dependencies in execution of the actual threads and re-executes instructions associated with the speculation errors from trace buffers outside an execution pipeline.

公开(公告)号：DE69829693D1

公开(公告)日：2005-05-12

申请号：DE69829693

申请日：1998-12-11

Applicant: INTEL CORP

Inventor： AKKARY HAITHAM ,  CHOW KINGSUM

IPC: G06F9/38 ,  G06F9/46 ,  G06F9/40

Abstract: In one embodiment, a processor includes thread management logic including a thread predictor having state machines to indicate whether thread creation opportunities should be taken or not taken. The processor includes a predictor training mechanism to receive retired instructions and to identify potential threads from the retired instructions and to determine whether a potential thread of interest meets a test of thread goodness, and if the test is met, one of the state machines that is associated with the potential thread of interest is updated in a take direction, and if the test is not met, the state machine is updated in a not take direction. The thread management logic may control creation of an actual thread and may further include reset logic to control whether the actual thread is reset and wherein if the actual thread is reset, one of the state machines associated with the actual thread is updated in a not take direction. The final retirement logic may control whether the actual thread is retired, and wherein if the actual thread is retired, the state machine associated with the actual thread is updated in a take direction. The circuitry may be used in connection with a multi-threading processor that detects speculation errors involving thread dependencies in execution of the actual threads and re-executes instructions associated with the speculation errors from trace buffers outside an execution pipeline.

公开(公告)号：DE69829693T2

公开(公告)日：2006-01-12

申请号：DE69829693

申请日：1998-12-11

Applicant: INTEL CORP

Inventor： AKKARY HAITHAM ,  CHOW KINGSUM

IPC: G06F9/38 ,  G06F9/40 ,  G06F9/46

Abstract: In one embodiment, a processor includes thread management logic including a thread predictor having state machines to indicate whether thread creation opportunities should be taken or not taken. The processor includes a predictor training mechanism to receive retired instructions and to identify potential threads from the retired instructions and to determine whether a potential thread of interest meets a test of thread goodness, and if the test is met, one of the state machines that is associated with the potential thread of interest is updated in a take direction, and if the test is not met, the state machine is updated in a not take direction. The thread management logic may control creation of an actual thread and may further include reset logic to control whether the actual thread is reset and wherein if the actual thread is reset, one of the state machines associated with the actual thread is updated in a not take direction. The final retirement logic may control whether the actual thread is retired, and wherein if the actual thread is retired, the state machine associated with the actual thread is updated in a take direction. The circuitry may be used in connection with a multi-threading processor that detects speculation errors involving thread dependencies in execution of the actual threads and re-executes instructions associated with the speculation errors from trace buffers outside an execution pipeline.

公开(公告)号：AU1913799A

公开(公告)日：1999-07-05

申请号：AU1913799

申请日：1998-12-11

Applicant: INTEL CORP

Inventor： AKKARY HAITHAM ,  CHOW KINGSUM

IPC: G06F9/38 ,  G06F9/46 ,  G06F9/30 ,  G06F9/40

Abstract: In one embodiment, a processor includes thread management logic including a thread predictor having state machines to indicate whether thread creation opportunities should be taken or not taken. The processor includes a predictor training mechanism to receive retired instructions and to identify potential threads from the retired instructions and to determine whether a potential thread of interest meets a test of thread goodness, and if the test is met, one of the state machines that is associated with the potential thread of interest is updated in a take direction, and if the test is not met, the state machine is updated in a not take direction. The thread management logic may control creation of an actual thread and may further include reset logic to control whether the actual thread is reset and wherein if the actual thread is reset, one of the state machines associated with the actual thread is updated in a not take direction. The final retirement logic may control whether the actual thread is retired, and wherein if the actual thread is retired, the state machine associated with the actual thread is updated in a take direction. The circuitry may be used in connection with a multi-threading processor that detects speculation errors involving thread dependencies in execution of the actual threads and re-executes instructions associated with the speculation errors from trace buffers outside an execution pipeline.

公开(公告)号：EP3049962A4

公开(公告)日：2017-04-12

申请号：EP13894295

申请日：2013-09-27

Applicant: INTEL CORP

Inventor： HUANG YICONG ,  CHOW KINGSUM

IPC: G06F17/30

CPC classification number: G06F17/30306 ,  G06F7/02 ,  G06F11/3037 ,  G06F11/3433 ,  G06F17/3007 ,  G06F17/30132 ,  G06F17/30221 ,  G06F17/3053 ,  G06F17/30598 ,  G06F17/30864 ,  G06F17/30943

Abstract: A mechanism is described for facilitating dynamic data management for computing devices according to one embodiment. A method of embodiments, as described herein, includes tracking one or more factors relating to a plurality of data sets, evaluating the plurality of data sets based on the one or more factors. The evaluating may include speculating at least one of relevancy and accessibility of each of the plurality of data sets. The method may further include generating data scores, the data scores being associated with the plurality of data sets based on the evaluation of the plurality of data sets, performing a first comparison of the data scores of the plurality of data sets with a criteria score, and classifying each data set based on the first comparison. The classifying may include setting caching order for each data set of the plurality of data sets.

公开(公告)号：EP2972894A4

公开(公告)日：2016-12-14

申请号：EP14769048

申请日：2014-03-13

Applicant: INTEL CORP

Inventor： WU KEQIANG ,  CHOW KINGSUM ,  LEE YONG-FONG

IPC: G06F12/08 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0815 ,  G06F12/0837

CPC classification number: G06F12/0802 ,  G06F12/0253 ,  G06F12/0815 ,  G06F12/0837

公开(公告)号：EP3022657A4

公开(公告)日：2017-03-15

申请号：EP13889446

申请日：2013-07-15

Applicant: INTEL CORP

Inventor： BAN KHUN ,  CHOW KINGSUM ,  AUNDHE SHIRISH ,  VISWANATHAN SANDHYA

IPC: G06F15/16

CPC classification number: G06F9/52 ,  G06F8/70 ,  G06F9/30076 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/528

Abstract: Various embodiments are generally directed to techniques for controlling the use of locks that regulate access to shared resources by concurrently executed portions of code. An apparatus to control locking of a resource includes a processor component, a history analyzer for execution by the processor component to analyze at least one result of a replacement of a lock instruction of a first instance of code with a lock marker to allow the processor component to speculatively execute a second instance of code, and a locking component for execution by the processor component to replace the lock instruction with the lock marker based on analysis of the at least one result, the first and second instances of code to access a resource and the lock instruction to request a lock of access to the resource to the first instance of code. Other embodiments are described and claimed.

公开(公告)号：EP1068570A4

公开(公告)日：2002-07-17

申请号：EP98963903

申请日：1998-12-11

Applicant: INTEL CORP

Inventor： AKKARY HAITHAM ,  CHOW KINGSUM

IPC: G06F9/38 ,  G06F9/46 ,  G06F9/40

CPC classification number: G06F9/3842 ,  G06F9/3013 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3863

Abstract: In one embodiment of the invention, a processor (50) includes an execution pipeline (108) to concurrently execute at least portions of threads T1-T4, wherein at least one of the threads is dependant on at least another one of the threads. The processor (50) also includes detection circuitry to detect speculation errors in the execution of the threads T1-T4. In another embodiment, the processor (50) includes thread management logic (124) to control dynamic creation of threads from a program (112A).