公开(公告)号：WO03027857A2

公开(公告)日：2003-04-03

申请号：PCT/US0231158

申请日：2002-09-27

Applicant: INTEL CORP

Inventor： LAI KONRAD ,  LU SHIH-LIEN ,  SOMASEKHAR DINESH

IPC: G06F12/08

CPC classification number: G06F12/0893

Abstract: The present invention is in the field of memory architecture and management. More particularly, the present invention provides a method, apparatus, system, and machine-readable medium to hide refresh cycles of a memory array such as dynamic random access memory.

Abstract translation: 本发明属于存储器体系结构和管理领域。 更具体地说，本发明提供了一种隐藏诸如动态随机存取存储器之类的存储器阵列的刷新周期的方法，装置，系统和机器可读介质。

公开(公告)号：WO0201366A3

公开(公告)日：2002-07-04

申请号：PCT/US0118683

申请日：2001-06-07

Applicant: INTEL CORP

Inventor： LAI KONRAD ,  WANG WEN-HANN ,  ROBINSON SCOTT ,  PEIR JIH-KWON ,  ZHANG STEVE

IPC: G06F12/08

CPC classification number: G06F12/0831

Abstract: The invention provides a cache management system comprising in various embodiment pre-load and pre-own functionality to enhance cache efficiency in shared memory distributed cache multiprocessor computer systems. Some embodiments of the invention comprise an invalidation history table to record the line addresses of cache lines invalidated through dirty or clean invalidation, and which is used such that invalidated cache lines recorded in an invalidation history table are reloaded into cache by monitoring the bus for cache line addresses of cache line recorded in the invalidation history table. In some further embodiments, a write-back bit associated with each L2 cache entry records when either a hit to the same line in another processor is detected or when the same line is invalidated in another processor's cache, and the system broadcasts write-backs from the selected local cache only when the line being written back has a write-back bit that has been set.

Abstract translation: 本发明提供了一种缓存管理系统，其在各种实施例中包括预加载和预先拥有的功能以增强共享存储器分布式缓存多处理器计算机系统中的缓存效率。 本发明的一些实施例包括用于记录通过脏或干净无效而失效的高速缓存行的行地址的无效历史表，并且其被使用使得通过监视总线高速缓存将记录在无效历史表中的无效高速缓存行重新加载到高速缓存中 记录在无效历史表中的缓存行的行地址。 在一些进一步的实施例中，当检测到到另一个处理器中的同一行的命中或当同一行在另一个处理器的高速缓存中被无效时，与每个L2高速缓存条目相关联的回写位记录，并且系统广播回写 只有在写回的行中有一个已设置的回写位时，才选择本地缓存。

公开(公告)号：WO9524678A3

公开(公告)日：1995-10-12

申请号：PCT/US9502505

申请日：1995-03-01

Applicant: INTEL CORP

Inventor： SARANGDHAR NITIN V ,  SINGH GURBIR ,  LAI KONRAD

IPC: G06F12/08 ,  G06F13/18 ,  G06F

CPC classification number: G06F13/18 ,  G06F12/0831

Abstract: A computer system (15) incorporating a pipelined bus (20) that maintains data coherency, supports long latency transactions and provides processor order is described. The computer system (15) includes bus agents (2, 4, 6, 8, 10, 12, 14) having in-order-queues (100) that track multiple outstanding transactions across a system bus (20) and that perform snoops in response to transaction requests, providing snoop results and modified data within one transaction. Additionally, the system (15) supports long latency transactions by providing deferred identifiers during transaction requests that are used to restart deferred transactions.

公开(公告)号：HK57590A

公开(公告)日：1990-08-10

申请号：HK57590

申请日：1990-08-02

Applicant: INTEL CORP

Inventor： MYERS GLENFORD J ,  LAI KONRAD ,  IMEI MICHAEL T ,  HINTON GLENN ,  RICHES ROBERT

IPC: G06F9/42 ,  G06F9/30 ,  G06F9/40 ,  G06F9/46 ,  G06F12/08

Abstract: A plurality of global registers are provided on the microprocessor chip. One of a global registers is a frame pointer register containing the current frame pointer, and the remainder of the global registers are available to a current process as general registers. A plurality of floating point registers are also provided for use by the current process in execution of floating point arithmetic operations. A register set pool made up of a plurality of register sets is provided, each register set being comprised of a number of local registers. When a call instruction is decoded, a register set of local registers from the register set pool is allocated to the called procedure, and the frame pointer register is initialized. When a return instruction is decoded, the register set is freed for allocation to another procedure called by a subsequent call instruction. If the register set pool is depleted a register set associated with a previous procedure is saved in the main memory, and that register set is allocated to the current procedure. The local registers in a register set associated with a procedure contain linkage information including a pointer to the previous frame and an instruction pointer, thus enabling most call and return instructions to execute without needing any references to off-chip memory.

公开(公告)号：GB2190521A

公开(公告)日：1987-11-18

申请号：GB8628175

申请日：1986-11-25

Applicant: INTEL CORP

Inventor： MYERS GLENFORD J ,  LAI KONRAD ,  IMEL MICHAEL T ,  HINTON GLENN ,  RICHES ROBERT

IPC: G06F9/42 ,  G06F9/30 ,  G06F9/40 ,  G06F9/46 ,  G06F12/08

Abstract: A plurality of global registers are provided on the microprocessor chip. One of a global registers is a frame pointer register containing the current frame pointer, and the remainder of the global registers are available to a current process as general registers. A plurality of floating point registers are also provided for use by the current process in execution of floating point arithmetic operations. A register set pool made up of a plurality of register sets is provided, each register set being comprised of a number of local registers. When a call instruction is decoded, a register set of local registers from the register set pool is allocated to the called procedure, and the frame pointer register is initialized. When a return instruction is decoded, the register set is freed for allocation to another procedure called by a subsequent call instruction. If the register set pool is depleted a register set associated with a previous procedure is saved in the main memory, and that register set is allocated to the current procedure. The local registers in a register set associated with a procedure contain linkage information including a pointer to the previous frame and an instruction pointer, thus enabling most call and return instructions to execute without needing any references to off-chip memory.

公开(公告)号：EP3014452A4

公开(公告)日：2017-04-26

申请号：EP13887960

申请日：2013-06-27

Applicant: INTEL CORP

Inventor： SCHMITT THILO ,  LACHNER PETER ,  STRONG BEEMAN ,  LEVY OFER ,  TOLL THOMAS ,  MERTEN MATTHEW ,  LI TONG ,  RAJWAR RAVI ,  LAI KONRAD

IPC: G06F11/36 ,  G06F9/30

CPC classification number: G06F9/30189 ,  G06F11/3636

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for tracking the mode of processing devices in an instruction tracing system. The method may include receiving an indication of a change in a current execution mode of the processing device. The method may also include determining that the current execution mode of the received indication is different than a value of an execution mode of a first execution mode (EM) packet previously-generated by the IT module. The method may also include generating, based on the determining that the current execution mode is different, a second EM packet that provides a value of the current execution mode of the processing device to indicate the change in the execution mode for an instruction in a trace generated by the IT module. The method may further include generating transactional memory (TMX) packets having n bit mode pattern in the packet log. The n is at least two and the n bit mode indicates transaction status of the TMX operation.

Abstract translation: 根据这里公开的实施例，提供了用于跟踪指令跟踪系统中处理设备的模式的系统和方法。 该方法可以包括接收处理设备的当前执行模式的改变的指示。 该方法还可以包括确定接收到的指示的当前执行模式不同于由IT模块先前生成的第一执行模式（EM）分组的执行模式的值。 该方法还可以包括基于确定当前执行模式是不同的第二EM分组来提供处理设备的当前执行模式的值以指示执行模式中的轨迹中的指令的改变 由IT模块生成。 该方法还可以包括在分组日志中生成具有n位模式模式的事务存储器（TMX）分组。 n至少为2，n位模式表示TMX操作的事务状态。

公开(公告)号：EP0748481A4

公开(公告)日：2000-07-05

申请号：EP95912647

申请日：1995-03-01

Applicant: INTEL CORP

Inventor： SARANGDHAR NITIN V ,  SINGH GURBIR ,  LAI KONRAD

IPC: G06F12/08 ,  G06F13/18 ,  G06F13/00

CPC classification number: G06F13/18 ,  G06F12/0831

Abstract: A computer system incorporating a pipelined bus that maintains data coherency, supports long latency transactions and provides processor order is described. The computer system includes bus agents having in-order-queues that track multiple outstanding transactions across a system bus and that perform snoops in response to transaction requests providing snoop results and modified data within one transaction. Additionally, the system supports long latency transactions by providing deferred identifiers during transaction requests that are used to restart deferred transactions.

公开(公告)号：GB2447200B

公开(公告)日：2011-06-22

申请号：GB0812727

申请日：2007-03-20

Applicant: INTEL CORP

Inventor： RAJWAR RAVI ,  AKKARY HAITHAM ,  LAI KONRAD

IPC: G06F9/46 ,  G06F9/44

Abstract: Methods and apparatus to provide transactional memory execution in out-of-order processors are described. In one embodiment, a stored value corresponds to the number of transactional memory access requests that are uncommitted. The stored value may be used to provide nested recovery in case of an error, fault, etc. in accordance with a described embodiment.

公开(公告)号：AU6681501A

公开(公告)日：2002-01-08

申请号：AU6681501

申请日：2001-06-07

Applicant: INTEL CORP

Inventor： LAI KONRAD ,  WANG WEN-HANN ,  ROBINSON SCOTT ,  PEIR JIH-KWON ,  ZHANG STEVE

IPC: G06F12/08 ,  G06F12/00

公开(公告)号：FR2598835A1

公开(公告)日：1987-11-20

申请号：FR8618432

申请日：1986-12-31

Applicant: INTEL CORP

Inventor： MYERS GLENFORD J ,  LAI KONRAD ,  IMEL MICHAEL T ,  HINTON GLENN ,  RICHES ROBERT

IPC: G06F9/42 ,  G06F9/30 ,  G06F9/40 ,  G06F9/46 ,  G06F12/08 ,  G06F12/00

Abstract: A plurality of global registers are provided on the microprocessor chip. One of a global registers is a frame pointer register containing the current frame pointer, and the remainder of the global registers are available to a current process as general registers. A plurality of floating point registers are also provided for use by the current process in execution of floating point arithmetic operations. A register set pool made up of a plurality of register sets is provided, each register set being comprised of a number of local registers. When a call instruction is decoded, a register set of local registers from the register set pool is allocated to the called procedure, and the frame pointer register is initialized. When a return instruction is decoded, the register set is freed for allocation to another procedure called by a subsequent call instruction. If the register set pool is depleted a register set associated with a previous procedure is saved in the main memory, and that register set is allocated to the current procedure. The local registers in a register set associated with a procedure contain linkage information including a pointer to the previous frame and an instruction pointer, thus enabling most call and return instructions to execute without needing any references to off-chip memory.