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公开(公告)号：JP2008117397A
公开(公告)日：2008-05-22
申请号：JP2007281947
申请日：2007-10-30
Applicant: Intel Corp , インテル コーポレイション
Inventor： GUNTHER STEPHEN , BURTON EDWARD A , DEVAL ANANT , JOURDAN STEPHAN , GREINER ROBERT , CORNABY MIKE
CPC classification number: G06F1/3234 , G06F1/3203 , G06F1/324 , G06F1/3287 , G06F1/3296
Abstract: PROBLEM TO BE SOLVED: To provide independent power control of two or more processing cores, more particularly, a technique to place at least one processing core in a certain power state without coordinating with the power state of one or more other processing cores in at least one embodiment.
SOLUTION: A power control logic for controlling power consumption of a first processing core independently from a second processing core is provided.
COPYRIGHT: (C)2008,JPO&INPITAbstract translation: 要解决的问题：为了提供两个或更多个处理核心的独立功率控制，更具体地，涉及将至少一个处理核心置于一定功率状态而不与一个或多个其它处理核心的功率状态协调的技术 在至少一个实施例中。 提供了一种用于独立于第二处理核心来控制第一处理核心的功耗的功率控制逻辑。 版权所有（C）2008，JPO＆INPIT
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公开(公告)号：WO0004595A3
公开(公告)日：2000-06-29
申请号：PCT/US9916067
申请日：1999-07-16
Applicant: INTEL CORP
Inventor： BURTON EDWARD A
CPC classification number: H05K1/0231 , H05K1/141 , H05K1/182 , H05K3/368 , H05K2201/049 , H05K2201/09072 , H05K2201/10378 , H05K2201/1053 , H05K2201/10636 , H05K2201/10704 , H05K2203/1572 , Y02P70/611
Abstract: A method and apparatus is presented to allow one or more electrical components to be coupled to the land-side of an integrated circuit package coupled to a circuit board. In a first embodiment, a void is provided in the circuit board, and a peripheral area of the integrated circuit package is coupled to a peripheral area around the void. This provides space for the insertion of components in the land-side of the integrated circuit package. In a second embodiment, a spacer is provided coupled to the peripheral area of the integrated circuit package to allow the insertion of components into the land-side of the package and above the circuit board. With these embodiments of the present invention, components, such as decoupling capacitors can be coupled closer to the die (e.g. a processor die) of the package thus reducing parasitic inductance.
Abstract translation: 提出了一种方法和设备，以允许一个或多个电气部件耦合到耦合到电路板的集成电路封装的焊盘侧。 在第一实施例中，在电路板中提供空隙，并且集成电路封装的外围区域耦合到空隙周围的外围区域。 这为在集成电路封装的焊盘侧插入元件提供了空间。 在第二实施例中，提供耦合到集成电路封装的外围区域的间隔件以允许将组件插入到封装的焊盘侧和电路板上方。 利用本发明的这些实施例，诸如去耦电容器的组件可以更靠近封装的管芯（例如，处理器管芯）耦合，从而降低寄生电感。
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公开(公告)号：WO0004753A3
公开(公告)日：2002-09-19
申请号：PCT/US9916121
申请日：1999-07-16
Applicant: INTEL CORP , BURTON EDWARD A
Inventor： BURTON EDWARD A
CPC classification number: H05K1/115 , H05K1/0231 , H05K1/114 , H05K3/4602 , H05K2201/0792 , H05K2201/09509 , H05K2201/09854
Abstract: An improvement is presented for connecting conductive components of a built-up circuit board. Rather than using vias or micro vias to connect a conductive layer to a conductive component separated by an insulating layer (56,58), an elongated via (60a,60b,60c,62a,62b,62c) is used. In one embodiment, the elongated via (62a,62b,62c) has a length that is sufficient to directly coupled a first layer (57) to the edge of a via (60a,60b,60c) in a lower layer. Thus, it can be said that the elongated via "self-aligns" with the via in the lower layer. In doing so, electrical connections from one side of a circuit board to a component coupled to the other side of the circuit board are more direct leading to a reduction in parasitic induction.
Abstract translation: 提出了用于连接积层电路板的导电部件的改进。 不是使用通孔或微通孔将导电层连接到由绝缘层（56,58）分离的导电部件，而是使用细长的通孔（60a，60b，60c，62a，62b，62c）。 在一个实施例中，细长通孔（62a，62b，62c）具有足以将第一层（57）直接耦合到下层中的通孔（60a，60b，60c）的边缘的长度。 因此，可以说细长通孔与下层中的通孔“自对准”。 在这样做时，从电路板的一侧到耦合到电路板的另一侧的部件的电连接更直接地导致寄生感应的减小。
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公开(公告)号：DE102014003670A1
公开(公告)日：2014-09-18
申请号：DE102014003670
申请日：2014-03-14
Applicant: INTEL CORP
Inventor： BURTON EDWARD A , SCHROM GERHARD , ROGERS MICHAEL W , LYAKHOV ALEXANDER , VUNNAM RAVI SANKAR , DOUGLAS JONATHAN P , PAILLET FABRICE , HODGSON J KEITH , KESLING DAWSON W , TANG CHIU KEUNG , RAGHURAMAN NARAYANAN , SAMAAN SAMIE , GEANNOPOULOS GEORGE L , NATARAJAN NARAYANAN
Abstract: Beschrieben ist eine Vorrichtung, die eine nichtlineare Steuerung zum Management des Leistungsversorgungsabfalls an einem Ausgang eines Spannungsreglers aufweist. Die Vorrichtung umfasst: eine erste Induktivität zum Koppeln mit einer Last; einen mit der ersten Induktivität gekoppelten Kondensator und zum Koppeln mit der Last; einen ersten mit der ersten Induktivität gekoppelten High-Side-Schalter; einen ersten mit der ersten Induktivität gekoppelten Low-Side-Schalter; eine Brückensteuerung zum Steuern, wann der erste High-Side-Schalter und der erste Low-Side-Schalter ein- und auszuschalten sind; und eine nicht lineare Steuerungseinheit (NLC) zum Überwachen der Ausgangsspannung an der Last und zum Veranlassen, dass die Brückensteuerung den ersten High-Side-Schalter einschaltet und den ersten Low-Side-Schalter ausschaltet, wenn ein Spannungsabfall an der Last detektiert wird.
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公开(公告)号：DE102014003791A1
公开(公告)日：2014-09-18
申请号：DE102014003791
申请日：2014-03-17
Applicant: INTEL CORP
Inventor： SCHROM GERHARD , HODGSON J KEITH , LYAKHOV ALEXANDER , TANG CHIU KEUNG , RAGHURAMAN NARAYANAN , NATARAJAN NARAYANAN , PAILLET FABRICE , SAMAAN SAMIE , VUNNAM RAVI SANKAR , ROGERS MICHAEL W , BURTON EDWARD A , DOUGLAS JONATHAN P , KESLING DAWSON W , GEANNOPOULOS GEORGE L
IPC: H02M3/158
Abstract: Beschrieben sind Vorrichtungen und Verfahren zum Stromausgleich, Stromabtastung und Phasenausgleich, Versatzeliminierung, Digital-zu-Analog-Stromwandlung mit monotoner Ausgabe unter Nutzung von binärkodierten Eingaben (ohne einen Binär-zu-Thermometer-Decoder), Kompensator für einen Spannungsregulator (VR), etc. In einem Beispiel umfasst die Vorrichtung: mehrere Induktivitäten, die an einen Kondensator und eine Last koppeln, mehrere Brücken, wovon jede gekoppelt ist an eine entsprechende Induktivität von den mehreren Induktivitäten; und mehrere Stromsensoren, wovon jeder gekoppelt ist an eine Brücke zum Abtasten eines Stromes durch einen Transistor der Brücke.
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Patent Agency Ranking
公开(公告)号：GB2440291A
公开(公告)日：2008-01-23
申请号：GB0721290
申请日：2007-10-30
Applicant: INTEL CORP
Inventor： BURTON EDWARD A , DEVAL ANANT
Abstract: In some embodiments, an error based supply regulation scheme is provided where error information from a cache is monitored, and the supply level supplying a CPU associated with the cache is controlled based on the error information. Other embodiments are disclosed herein.
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公开(公告)号：GB2444597B
公开(公告)日：2010-12-22
申请号：GB0721314
申请日：2007-10-30
Applicant: INTEL CORP
Inventor： GUNTHER STEPHEN H , BURTON EDWARD A , DEVAL ANANT , JOURDAN STEPHAN , GREINER ROBERT J , CORNABY MIKE
IPC: G06F1/32
Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.
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公开(公告)号：GB2356977B
公开(公告)日：2003-06-04
申请号：GB0030348
申请日：1999-07-16
Applicant: INTEL CORP
Inventor： BURTON EDWARD A
Abstract: An improvement is presented for connecting conductive components of a built-up circuit board. Rather than using vias or micro vias to connect a conductive layer to a conductive component separated by an insulating layer, an elongated via is used. In one embodiment, the elongated via has a length that is sufficient to directly coupled a first layer to the edge of a via in a lower layer. Thus, it can be said that the elongated via "self-aligns" with the via in the lower layer. In doing so, electrical connections from one side of a circuit board to a component coupled to the other side of the circuit board are more direct leading to a reduction in parasitic induction.
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公开(公告)号：DE19983389T1
公开(公告)日：2003-03-27
申请号：DE19983389
申请日：1999-07-16
Applicant: INTEL CORP
Inventor： BURTON EDWARD A
Abstract: An improvement is presented for connecting conductive components of a built-up circuit board. Rather than using vias or micro vias to connect a conductive layer to a conductive component separated by an insulating layer, an elongated via is used. In one embodiment, the elongated via has a length that is sufficient to directly coupled a first layer to the edge of a via in a lower layer. Thus, it can be said that the elongated via "self-aligns" with the via in the lower layer. In doing so, electrical connections from one side of a circuit board to a component coupled to the other side of the circuit board are more direct leading to a reduction in parasitic induction.
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公开(公告)号：GB2440291B
公开(公告)日：2010-03-24
申请号：GB0721290
申请日：2007-10-30
Applicant: INTEL CORP
Inventor： BURTON EDWARD A , DEVAL ANANT
Abstract: In some embodiments, an error based supply regulation scheme is provided where error information from a cache is monitored, and the supply level supplying a CPU associated with the cache is controlled based on the error information. Other embodiments are disclosed herein.
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