公开(公告)号：AU2884599A

公开(公告)日：1999-09-27

申请号：AU2884599

申请日：1999-02-26

Applicant: INTEL CORP

Inventor： WU YOUFENG ,  LEE YONG-FONG

IPC: G06F9/38 ,  G06F9/45

Abstract: In one implementation of the invention, a computer implemented method used in compiling a program includes identifying a covering load, which may be one of a set of covering loads, and a redundant load. The covering load and the redundant load have a first and second load type, respectively. The first and the second load type each may be one of a group of load types including a regular load and at least one speculative-type load. In one implementation, the group of load types includes at least one check-type load. One implementation of the invention is in a machine readable medium.

公开(公告)号：EP1062576A4

公开(公告)日：2003-08-27

申请号：EP99909696

申请日：1999-02-26

Applicant: INTEL CORP

Inventor： WU YOUFENG ,  LEE YONG-FONG

IPC: G06F9/38 ,  G06F9/45

CPC classification number: G06F8/433 ,  G06F8/443 ,  G06F8/445 ,  G06F9/383 ,  G06F9/3842

Abstract: In one implementation of the invention, a computer implemented method used in compiling a program includes identifying a covering load, which may be one of a set of covering loads, and a redundant load. The covering load and the redundant load have a first and second load type, respectively. The first and the second load type each may be one of a group of load types including a regular load and at least one speculative-type load. In one implementation, the group of load types includes at least one check-type load. One implementation of the invention is in a machine readable medium.

公开(公告)号：EP3230878A4

公开(公告)日：2018-07-25

申请号：EP15867831

申请日：2015-11-13

Applicant: INTEL CORP

Inventor： WU KEQIANG ,  LU JIWEI ,  LEE YONG-FONG

IPC: G06F13/16 ,  G06F8/52 ,  G06F8/70 ,  G06F9/30 ,  G06F11/30 ,  G06F11/34 ,  G06F13/14

CPC classification number: G06F9/30065 ,  G06F8/52 ,  G06F8/70 ,  G06F9/30087 ,  G06F11/3024 ,  G06F11/3409 ,  G06F11/3466 ,  G06F2201/81 ,  G06F2201/825 ,  G06F2201/865 ,  G06F2201/88

Abstract: One embodiment provides an apparatus. The apparatus includes a processor, a chipset, a memory to store a process, and logic. The processor includes one or more core(s) and is to execute the process. The logic is to acquire performance monitoring data in response to a platform processor utilization parameter (PUP) greater than a detection utilization threshold (UT), identify a spin loop based, at least in part, on at least one of a detected hot function and/or a detected hot loop, modify the identified spin loop using binary translation to create a modified process portion, and implement redirection from the identified spin loop to the modified process portion.

公开(公告)号：EP2972894A4

公开(公告)日：2016-12-14

申请号：EP14769048

申请日：2014-03-13

Applicant: INTEL CORP

Inventor： WU KEQIANG ,  CHOW KINGSUM ,  LEE YONG-FONG

IPC: G06F12/08 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0815 ,  G06F12/0837

CPC classification number: G06F12/0802 ,  G06F12/0253 ,  G06F12/0815 ,  G06F12/0837