公开(公告)号：WO2004046920A2

公开(公告)日：2004-06-03

申请号：PCT/US0334808

申请日：2003-10-30

Applicant: INTEL CORP

Inventor： DATTA SHAM ,  ZIMMER VINCENT ,  VAID KUSHAGRA ,  STEVENS WILLIAM ,  SANTONI AMY

IPC: G06F9/445 ,  G06F12/08 ,  G06F12/12

CPC classification number: G06F12/126 ,  G06F9/4403 ,  G06F12/0862 ,  G06F2212/2515

Abstract: In one embodiment, a computer boot method allows choosing a predetermined data block alignment for a cache that has multiple cross processor interactions. A cache RAM column of a cache as RAM system is loaded with a tag to prevent unintended cache line evictions, and boot code is executed, with the preloaded cache RAM appearing to the exe­cuting boot code stream as a memory store.

Abstract translation: 在一个实施例中，计算机引导方法允许为具有多个交叉处理器交互的高速缓存选择预定数据块对齐。 作为RAM系统的缓存的高速缓存RAM列被加载有标签以防止意外的高速缓存行驱逐，并且执行引导代码，其中预先加载的高速缓存RAM作为存储器存储器显示在执行的引导代码流中。

公开(公告)号：GB2359166B

公开(公告)日：2003-05-14

申请号：GB0112361

申请日：1999-11-04

Applicant: INTEL CORP

Inventor： DATTA SHAM

IPC: G06F9/445 ,  G06F9/455 ,  G06F3/00

Abstract: A firmware system comprises a legacy firmware module and a native firmware module written for native and legacy instruction set architectures (ISAs), respectively. A data structure is associated with the legacy firmware module to provide access to one or more legacy routines through a first dispatcher. The native firmware nodule includes a prologue routine. The prolog routine locates the data structure associated with the legacy firmware module and initializes it to provide a link between the first and second firmware modules.

公开(公告)号：DE19983768T1

公开(公告)日：2001-11-29

申请号：DE19983768

申请日：1999-11-04

Applicant: INTEL CORP

Inventor： DATTA SHAM

IPC: G06F9/445 ,  G06F9/455 ,  G06F3/00

Abstract: A firmware system comprises a legacy firmware module and a native firmware module written for native and legacy instruction set architectures (ISAs), respectively. A data structure is associated with the legacy firmware module to provide access to one or more legacy routines through a first dispatcher. The native firmware nodule includes a prologue routine. The prolog routine locates the data structure associated with the legacy firmware module and initializes it to provide a link between the first and second firmware modules.

公开(公告)号：GB2359166A

公开(公告)日：2001-08-15

申请号：GB0112361

申请日：1999-11-04

Applicant: INTEL CORP

Inventor： DATTA SHAM

IPC: G06F9/445 ,  G06F9/455 ,  G06F3/00

Abstract: A firmware system (204, 208) comprises a legacy firmware module (204) and a native firmware module (208) written for native and legacy instruction set architectures (ISAs), respectively. A data structure (234) is associated with the legacy firmware module to provide access to one or more legacy routines (210) through a first dispatcher (220). The native firmware module includes a prolog routine (250). The prolog routine locates the data structure associated with the legacy firmware module and initializes it to provide a link between the first and second firmware modules.

公开(公告)号：AU1344000A

公开(公告)日：2000-06-19

申请号：AU1344000

申请日：1999-11-04

Applicant: INTEL CORP

Inventor： DATTA SHAM

IPC: G06F9/445 ,  G06F9/455 ,  G06F3/00

Abstract: A firmware system comprises a legacy firmware module and a native firmware module written for native and legacy instruction set architectures (ISAs), respectively. A data structure is associated with the legacy firmware module to provide access to one or more legacy routines through a first dispatcher. The native firmware nodule includes a prologue routine. The prolog routine locates the data structure associated with the legacy firmware module and initializes it to provide a link between the first and second firmware modules.

公开(公告)号：AU2003287426A1

公开(公告)日：2004-06-15

申请号：AU2003287426

申请日：2003-10-30

Applicant: INTEL CORP

Inventor： ZIMMER VINCENT ,  VAID KUSHAGRA ,  STEVENS WILLIAM ,  SANTONI AMY ,  DATTA SHAM

IPC: G06F9/445 ,  G06F12/08 ,  G06F12/12

Abstract: In one embodiment, a computer boot method allows choosing a predetermined data block alignment for a cache that has multiple cross processor interactions. A cache RAM column of a cache as RAM system is loaded with a tag to prevent unintended cache line evictions, and boot code is executed, with the preloaded cache RAM appearing to the executing boot code stream as a memory store.

公开(公告)号：DE69531460D1

公开(公告)日：2003-09-11

申请号：DE69531460

申请日：1995-02-24

Applicant: INTEL CORP

Inventor： DATTA SHAM ,  JOSHI JAYESH ,  KARDACH P

IPC: G06F1/32 ,  G06F13/42 ,  G06F13/00

公开(公告)号：HK1074501A1

公开(公告)日：2005-11-11

申请号：HK05106116

申请日：2005-07-19

Applicant: INTEL CORP

Inventor： DATTA SHAM ,  ZIMMER VINCENT ,  VAID KUSHAGRA ,  STEVENS WILLIAM A ,  SANTONI AMY

IPC: G06F20060101 ,  G06F9/445 ,  G06F12/08 ,  G06F12/12

Abstract: In one embodiment, a computer boot method allows choosing a predetermined data block alignment for a cache that has multiple cross processor interactions. A cache RAM column of a cache as RAM system is loaded with a tag to prevent unintended cache line evictions, and boot code is executed, with the preloaded cache RAM appearing to the executing boot code stream as a memory store.

公开(公告)号：DE69531460T2

公开(公告)日：2004-06-24

申请号：DE69531460

申请日：1995-02-24

Applicant: INTEL CORP

Inventor： DATTA SHAM ,  JOSHI JAYESH ,  KARDACH P

IPC: G06F1/32 ,  G06F13/42 ,  G06F13/00

公开(公告)号：EP0811197A4

公开(公告)日：1999-11-24

申请号：EP95911910

申请日：1995-02-24

Applicant: INTEL CORP

Inventor： DATTA SHAM ,  JOSHI JAYESH ,  KARDACH JAMES P

IPC: G06F1/32 ,  G06F13/42 ,  G06F13/00

CPC classification number: G06F1/3215 ,  G06F13/423

Abstract: A device and method for transferring data, address and status information concerning a former I/O bus cycle before a system management interrupt is initiated. A plurality of system management shadow registers (22) samples information from a system bus (16). Such information is obtained by a register accessing the plurality of system management shadow registers (22) through a common shadow port.