公开(公告)号：GB2408821A

公开(公告)日：2005-06-08

申请号：GB0504086

申请日：2003-09-05

Applicant: INTEL CORP

Inventor： SCHELLING TODD ,  SANTONI AMY ,  VALINE CRAIG ,  GREENE WILLIAM ,  ELKHOURY BASSAM ,  LOVELACE JOHN ,  O'SHEA DAVID

IPC: G06F9/445

Abstract: One embodiment of the invention provides a firmware architecture which splits firmware modules to support safe updates of specific modules as well as supporting multiple different processors. A firmware image is partitioned into several different binaries based on their update requirements and processor/platform dependence. A firmware interface table enables safe updates by enabling the option of redundant copies of specific modules as well as supporting systems with different and/or multiple processor types, mixed processors from the same family, and/or fault resilient firmware updates.

公开(公告)号：WO2004046920A2

公开(公告)日：2004-06-03

申请号：PCT/US0334808

申请日：2003-10-30

Applicant: INTEL CORP

Inventor： DATTA SHAM ,  ZIMMER VINCENT ,  VAID KUSHAGRA ,  STEVENS WILLIAM ,  SANTONI AMY

IPC: G06F9/445 ,  G06F12/08 ,  G06F12/12

CPC classification number: G06F12/126 ,  G06F9/4403 ,  G06F12/0862 ,  G06F2212/2515

Abstract: In one embodiment, a computer boot method allows choosing a predetermined data block alignment for a cache that has multiple cross processor interactions. A cache RAM column of a cache as RAM system is loaded with a tag to prevent unintended cache line evictions, and boot code is executed, with the preloaded cache RAM appearing to the exe­cuting boot code stream as a memory store.

Abstract translation: 在一个实施例中，计算机引导方法允许为具有多个交叉处理器交互的高速缓存选择预定数据块对齐。 作为RAM系统的缓存的高速缓存RAM列被加载有标签以防止意外的高速缓存行驱逐，并且执行引导代码，其中预先加载的高速缓存RAM作为存储器存储器显示在执行的引导代码流中。

公开(公告)号：WO2004023289A3

公开(公告)日：2005-03-03

申请号：PCT/US0327791

申请日：2003-09-05

Applicant: INTEL CORP

Inventor： SCHELLING TODD ,  SANTONI AMY ,  VALINE CRAIG ,  GREENE WILLIAM ,  ELKHOURY BASSAM ,  LOVELACE JOHN ,  O'SHEA DAVID

IPC: G06F9/445 ,  G06F11/14

CPC classification number: G06F9/44547 ,  G06F8/65

Abstract: One embodiment of the invention provides a firmware architecture which splits firmware modules to support safe updates of specific modules as well as supporting multiple different processors. A firmware image is partitioned into several different binaries based on their update requirements and processor/platform dependence. A firmware interface table enables safe updates by enabling the option of redundant copies of specific modules as well as supporting systems with different and/or multiple processor types, mixed processors from the same family, and/or fault resilient firmware updates.

Abstract translation: 本发明的一个实施例提供一种固件架构，其分解固件模块以支持特定模块的安全更新以及支持多个不同的处理器。 固件映像根据其更新要求和处理器/平台依赖性分为几个不同的二进制文件。 通过启用特定模块的冗余副本以及支持具有不同和/或多种处理器类型的系统，来自同一系列的混合处理器和/或故障恢复固件更新的固件接口表，可实现安全更新。

公开(公告)号：HK1074501A1

公开(公告)日：2005-11-11

申请号：HK05106116

申请日：2005-07-19

Applicant: INTEL CORP

Inventor： DATTA SHAM ,  ZIMMER VINCENT ,  VAID KUSHAGRA ,  STEVENS WILLIAM A ,  SANTONI AMY

IPC: G06F20060101 ,  G06F9/445 ,  G06F12/08 ,  G06F12/12

Abstract: In one embodiment, a computer boot method allows choosing a predetermined data block alignment for a cache that has multiple cross processor interactions. A cache RAM column of a cache as RAM system is loaded with a tag to prevent unintended cache line evictions, and boot code is executed, with the preloaded cache RAM appearing to the executing boot code stream as a memory store.

公开(公告)号：DE102018115491A1

公开(公告)日：2019-03-28

申请号：DE102018115491

申请日：2018-06-27

Applicant: INTEL CORP

Inventor： NEIGER GILBERT ,  PATEL BAIJU ,  SCHOINAS IOANNIS ,  SAHITA RAVI ,  DURHAM DAVID ,  KHOSRAVI HORMUZD ,  SANTONI AMY ,  OUZIEL IDO ,  SANKARAN RAJESH ,  GERZON GIDEON ,  CHHABRA SIDDHARTHA ,  HUNTLEY BARRY

IPC: G06F21/72 ,  G06F12/14

Abstract: In einer Ausführungsform ist eine kryptographische Schaltung dazu eingerichtet, in Reaktion auf eine Leseanforderung mit einer Speicheradresse von einem ersten Agenten, eine Datenzeile mit zumindest einem verschlüsselten Abschnitt aus einem Speicher zu empfangen, eine Schlüsselkennung für einen Schlüssel des ersten Agenten aus der Datenzeile zu erhalten, den Schlüssel unter Verwendung der Schlüsselkennung zu erhalten, den zumindest verschlüsselten Abschnitt der Datenzeile unter Verwendung des Schlüssels zu entschlüsseln, und entschlüsselte Daten des zumindest verschlüsselten Abschnitts der Datenzeile an den ersten Agenten zu senden. Weitere Ausführungsformen werden beschrieben und beansprucht.

公开(公告)号：AU2003287426A1

公开(公告)日：2004-06-15

申请号：AU2003287426

申请日：2003-10-30

Applicant: INTEL CORP

Inventor： ZIMMER VINCENT ,  VAID KUSHAGRA ,  STEVENS WILLIAM ,  SANTONI AMY ,  DATTA SHAM

IPC: G06F9/445 ,  G06F12/08 ,  G06F12/12

Abstract: In one embodiment, a computer boot method allows choosing a predetermined data block alignment for a cache that has multiple cross processor interactions. A cache RAM column of a cache as RAM system is loaded with a tag to prevent unintended cache line evictions, and boot code is executed, with the preloaded cache RAM appearing to the executing boot code stream as a memory store.

公开(公告)号：AU2003273286A1

公开(公告)日：2004-03-29

申请号：AU2003273286

申请日：2003-09-05

Applicant: INTEL CORP

Inventor： SCHELLING TODD ,  SANTONI AMY ,  VALINE CRAIG ,  GREENE WILLIAM ,  ELKHOURY BASSAM ,  LOVELACE JOHN ,  O'SHEA DAVID

IPC: G06F9/445 ,  G06F9/00

Abstract: One embodiment of the invention provides a firmware architecture which splits firmware modules to support safe updates of specific modules as well as supporting multiple different processors. A firmware image is partitioned into several different binaries based on their update requirements and processor/platform dependence. A firmware interface table enables safe updates by enabling the option of redundant copies of specific modules as well as supporting systems with different and/or multiple processor types, mixed processors from the same family, and/or fault resilient firmware updates.

公开(公告)号：DE10393727T5

公开(公告)日：2006-09-28

申请号：DE10393727

申请日：2003-10-30

Applicant: INTEL CORP

Inventor： DATTA SHAM ,  ZIMMER VINCENT ,  VAID KUSHAGRA ,  STEVENS WILLIAM ,  SANTONI AMY

IPC: G06F9/445 ,  G06F12/08 ,  G06F12/12

Abstract: In one embodiment, a computer boot method allows choosing a predetermined data block alignment for a cache that has multiple cross processor interactions. A cache RAM column of a cache as RAM system is loaded with a tag to prevent unintended cache line evictions, and boot code is executed, with the preloaded cache RAM appearing to the executing boot code stream as a memory store.

公开(公告)号：GB2409747B

公开(公告)日：2006-09-20

申请号：GB0506998

申请日：2003-10-30

Applicant: INTEL CORP

Inventor： DATTA SHAM ,  ZIMMER VINCENT ,  VAID KUSHAGRA ,  STEVENS WILLIAM A ,  SANTONI AMY

IPC: G06F12/12 ,  G06F9/445 ,  G06F12/08

Abstract: In one embodiment, a computer boot method allows choosing a predetermined data block alignment for a cache that has multiple cross processor interactions. A cache RAM column of a cache as RAM system is loaded with a tag to prevent unintended cache line evictions, and boot code is executed, with the preloaded cache RAM appearing to the executing boot code stream as a memory store.

公开(公告)号：GB2408821B

公开(公告)日：2006-04-12

申请号：GB0504086

申请日：2003-09-05

Applicant: INTEL CORP

Inventor： SCHELLING TODD ,  SANTONI AMY ,  VALINE CRAIG ,  GREENE WILLIAM ,  ELKHOURY BASSAM ,  LOVELACE JOHN ,  O'SHEA DAVID

IPC: G06F11/14 ,  G06F9/445

Abstract: One embodiment of the invention provides a firmware architecture which splits firmware modules to support safe updates of specific modules as well as supporting multiple different processors. A firmware image is partitioned into several different binaries based on their update requirements and processor/platform dependence. A firmware interface table enables safe updates by enabling the option of redundant copies of specific modules as well as supporting systems with different and/or multiple processor types, mixed processors from the same family, and/or fault resilient firmware updates.