公开(公告)号：AU4521200A

公开(公告)日：2000-07-24

申请号：AU4521200

申请日：1999-12-08

Applicant: INTEL CORP

Inventor： MAKINENI SIVAKUMAR ,  KIMN SUNNHYUK ,  DOSHI GAUTMAN B ,  GOLLIVER ROGER A

IPC: G06F9/30 ,  G06F9/302 ,  G06F9/318

Abstract: A method is provided for loading a packed floating-point operand into a register file entry having one or more associated implicit bits. The packed floating point operand includes multiple component operands. Significand and exponent bits for each component operand are copied to corresponding fields of the register entry, and the exponent bits are tested to determine whether the component operand is normalized. An implicit bit corresponding to the component operand is set when the component operand is normalized.

公开(公告)号：GB2510792A

公开(公告)日：2014-08-20

申请号：GB201122094

申请日：2010-08-02

Applicant: INTEL CORP

Inventor： NATU MAHESH S ,  GANESAN BASKARAN ,  RANGARAJAN THANUMATHAN ,  KUMAR MOHAN J ,  DOSHI GAUTMAN B ,  PARTHASARATHY RAJESH S ,  DATTA SHAMMANNA M ,  BINNS FRANK ,  MURTHY RAJESH NAGARAJA ,  SWANSON ROBERT C

IPC: G06F9/48

Abstract: In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.

公开(公告)号：DE19983870T1

公开(公告)日：2002-04-11

申请号：DE19983870

申请日：1999-12-08

Applicant: INTEL CORP

Inventor： MAKINENI SIVAKUMAR ,  KIMN SNNHYUK ,  DOSHI GAUTMAN B ,  GOLLIVER ROGER A

IPC: G06F9/30 ,  G06F9/302 ,  G06F9/318

Abstract: A method is provided for loading a packed floating-point operand into a register file entry having one or more associated implicit bits. The packed floating point operand includes multiple component operands. Significand and exponent bits for each component operand are copied to corresponding fields of the register entry, and the exponent bits are tested to determine whether the component operand is normalized. An implicit bit corresponding to the component operand is set when the component operand is normalized.

公开(公告)号：GB2360110A

公开(公告)日：2001-09-12

申请号：GB0114436

申请日：1999-12-08

Applicant: INTEL CORP

Inventor： MAKINENI SIVAKUMAR ,  KIMN SNNHYUK ,  DOSHI GAUTMAN B ,  GOLLIVER ROGER A

IPC: G06F9/30 ,  G06F9/302 ,  G06F9/318

Abstract: A method is provided for loading a packed floating-point operand into a register file entry having one or more associated implicit bits. The packed floating point operand includes multiple component operands. Significand and exponent bits for each component operand are copied to corresponding fields of the register entry, and the exponent bits are tested to determine whether the component operand is normalized. An implicit bit corresponding to the component operand is set when the component operand is normalized.

公开(公告)号：DE19983870B4

公开(公告)日：2005-05-19

申请号：DE19983870

申请日：1999-12-08

Applicant: INTEL CORP

Inventor： MAKINENI SIVAKUMAR ,  KIMN SNNHYUK ,  DOSHI GAUTMAN B ,  GOLLIVER ROGER A

IPC: G06F9/30 ,  G06F9/302 ,  G06F9/318

Abstract: A method is provided for loading a packed floating-point operand into a register file entry having one or more associated implicit bits. The packed floating point operand includes multiple component operands. Significand and exponent bits for each component operand are copied to corresponding fields of the register entry, and the exponent bits are tested to determine whether the component operand is normalized. An implicit bit corresponding to the component operand is set when the component operand is normalized.

公开(公告)号：GB2360110B

公开(公告)日：2003-05-21

申请号：GB0114436

申请日：1999-12-08

Applicant: INTEL CORP

Inventor： MAKINENI SIVAKUMAR ,  KIMN SNNHYUK ,  DOSHI GAUTMAN B ,  GOLLIVER ROGER A

IPC: G06F9/30 ,  G06F9/302 ,  G06F9/318

Abstract: A method is provided for loading a packed floating-point operand into a register file entry having one or more associated implicit bits. The packed floating point operand includes multiple component operands. Significand and exponent bits for each component operand are copied to corresponding fields of the register entry, and the exponent bits are tested to determine whether the component operand is normalized. An implicit bit corresponding to the component operand is set when the component operand is normalized.