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    DATA ERROR RECOVERY IN NON-VOLATILE MEMORY
    1.
    发明申请
    DATA ERROR RECOVERY IN NON-VOLATILE MEMORY 审中-公开
    数据错误恢复在非易失性存储器中

    公开(公告)号：WO2010080257A3

    公开(公告)日：2010-09-02

    申请号：PCT/US2009066612

    申请日：2009-12-03

    Applicant: INTEL CORP ,  COULSON RICHARD ,  FAZIO ALBERT ,  KHAN JAWAD

    Inventor： COULSON RICHARD ,  FAZIO ALBERT ,  KHAN JAWAD

    IPC: G06F11/08 ,  G06F12/16

    CPC classification number: G11C16/3404 ,  G06F11/1068 ,  G11C29/52 ,  G11C2029/0411

    Abstract: When an error correction code (ECC) unit finds uncorrectable errors in a solid state non-volatile memory device, a process may be used in an attempt to locate and correct the errors. This process may first identify 'low confidence' memory cells that are likely to contain errors, and then determine what data is more likely to be correct in those cells, based on various criteria. The new data may then be checked with the ECC unit to verify that it is sufficiently correct for the ECC unit to correct any remaining errors.

    Abstract translation: 当纠错码（ECC）单元在固态非易失性存储器件中发现不可纠正的错误时，可以使用一个过程来尝试定位和校正错误。 该过程可以首先识别可能包含错误的“低置信度”存储器单元，然后基于各种标准确定哪些数据在这些单元中更可能是正确的。 然后可以用ECC单元检查新数据，以验证ECC单元足够正确以校正任何剩余的错误。

    MEMS PROBE BASED MEMORY
    2.
    发明申请
    MEMS PROBE BASED MEMORY 审中-公开
    基于MEMS探针的存储器

    公开(公告)号：WO2006071834A3

    公开(公告)日：2006-08-17

    申请号：PCT/US2005046990

    申请日：2005-12-21

    Applicant: INTEL CORP ,  LAI STEFAN ,  FAZIO ALBERT ,  RAO VALLURI ,  BROWN MIKE ,  MURALI KRISNAMURTHY

    Inventor： LAI STEFAN ,  FAZIO ALBERT ,  RAO VALLURI ,  BROWN MIKE ,  MURALI KRISNAMURTHY

    IPC: G11B9/00

    CPC classification number: G11C23/00 ,  B82Y10/00 ,  G11B9/1436 ,  G11B9/149 ,  G11C13/0004

    Abstract: In accordance with one embodiment of the invention, a memory device may include a memory layer and a MEMS layer. The memory layer may include an integrated circuit with a multiplexer and optionally a memory controller and a storage medium disposed on the integrated circuit where the storage medium includes chalcogenide islands as storage elements. The MEMS layer may include a movable MEMS platform having probes to connect selected chalcogenide islands via positioning of the MEMS platform. A high voltage source disposed external to the memory layer and the MEMS layer may provide a high voltage to a stator electrode on the memory layer and to a rotor electrode on the MEMS platform to control movement of the MEMS platform with respect to the storage medium. The memory device may be utilized in portable electronic devices such as media players and cellular telephones to provide a nonvolatile storage of information.

    Abstract translation: 根据本发明的一个实施例，存储器件可以包括存储器层和MEMS层。 存储器层可以包括具有多路复用器和可选地存储器控制器的集成电路和布置在集成电路上的存储介质，其中存储介质包括作为存储元件的硫族化物岛。 MEMS层可以包括具有通过MEMS平台的定位连接选定的硫族化物岛的探针的可移动MEMS平台。 设置在存储器层和MEMS层外部的高电压源可以向存储器层上的定子电极和MEMS平台上的转子电极提供高电压，以控制MEMS平台相对于存储介质的移动。 存储装置可以用于诸如媒体播放器和蜂窝电话的便携式电子设备中，以提供信息的非易失性存储。

    PROGRAMMING FLASH MEMORY USING DISTRIBUTED LEARNING METHODS
    3.
    发明公开
    PROGRAMMING FLASH MEMORY USING DISTRIBUTED LEARNING METHODS 失效
    编程快闪内存分布式学习

    公开(公告)号：EP0886864A1

    公开(公告)日：1998-12-30

    申请号：EP96943732

    申请日：1996-12-10

    Applicant: INTEL CORP

    Inventor： FAZIO ALBERT ,  ATWOOD GREGORY E ,  MI JAMES Q ,  RUBY PAUL

    IPC: G11C11/56 ,  G11C11/34 ,  G11C27/00

    CPC classification number: G11C11/5628 ,  G11C11/5621

    Abstract: In a memory device including an array of memory cells, each memory cell having more than two possible states, a method for programming a memory cell to a desired state is disclosed. The method comprises a control engine programming a subset (220), wherein the characterization information indicates programming characteristics of a representative memory cell of the array of memory cells (225). The control engine then uses the characterization information to directly program the memory cell to approximately the desired state (230) without performing a program verify operation.

    ESQUEMAS DE DETECCION PARA MEMORIA FLASH CON CELDAS DE MULTIPLES NIVELES.
    6.
    发明专利
    ESQUEMAS DE DETECCION PARA MEMORIA FLASH CON CELDAS DE MULTIPLES NIVELES. 未知

    公开(公告)号：MX9604972A

    公开(公告)日：1998-02-28

    申请号：MX9604972

    申请日：1995-05-18

    Applicant: INTEL CORP

    Inventor： BAUER MARK E ,  TALREJA SANJAY ,  FAZIO ALBERT ,  ATWOOD GREGORY ,  JAVANIFARD JOHNNY ,  FRARY KEVIN

    Abstract: Se describen método y aparatos para determinar el estado de una celda de memoria que tiene más de dos estados posibles. Para una primer modalidad, el estado de una celda flash (401??) que tiene n estados, en donde n es una potencia de dos, se determina al comparar selectivamente el voltaje umbral Vt de una celda de memoria selecta con (n-1) voltajes de referencia. Por cada dos estados, se proporciona un solo comparador (460 y 470), de manera tal que el numero total de comparadores sea igual al numero de bits almacenados en la celda de memoria.

    7.
    发明专利
    未知

    公开(公告)号：BR9507833A

    公开(公告)日：1997-09-16

    申请号：BR9507833

    申请日：1995-05-04

    Applicant: INTEL CORP

    Inventor： TEDROW KERRY ,  KEENEY STEPHEN ,  FAZIO ALBERT ,  ATWOOD GREGORY ,  JAVANIFARD JOHNNY ,  WOJCIECHOWSKI KENNETH

    IPC: G05F1/46 ,  G11C5/14 ,  G11C11/56 ,  G11C16/30 ,  G05F1/10 ,  H03K3/02 ,  H03K5/22

    Abstract: A voltage regulation circuit that includes a sample and hold circuit for sampling an input voltage and for holding a reference voltage generated in response to the input voltage. The sample and hold circuit includes a capacitor that holds the reference voltage. The voltage regulation circuit also includes a regulator circuit coupled to the capacitor of the sample and hold circuit. The regulator circuit outputs an output voltage using the reference voltage supplied by the capacitor. The voltage regulation circuit may be used to provide a high precision programming voltage for programming memory cells having two or more analog states.

    9.
    发明专利
    未知

    公开(公告)号：DE69533858D1

    公开(公告)日：2005-01-20

    申请号：DE69533858

    申请日：1995-05-04

    Applicant: INTEL CORP

    Inventor： TEDROW KERRY ,  KEENEY STEPHEN ,  FAZIO ALBERT ,  ATWOOD GREGORY ,  JAVANIFARD JOHNNY ,  WOJCIECHOWSKI KENNETH

    IPC: G05F1/46 ,  G11C5/14 ,  G11C11/56 ,  G11C16/30 ,  G05F1/10 ,  H03K3/02 ,  H03K5/22

    Abstract: A voltage regulation circuit that includes a sample and hold circuit for sampling an input voltage and for holding a reference voltage generated in response to the input voltage. The sample and hold circuit includes a capacitor that holds the reference voltage. The voltage regulation circuit also includes a regulator circuit coupled to the capacitor of the sample and hold circuit. The regulator circuit outputs an output voltage using the reference voltage supplied by the capacitor. The voltage regulation circuit may be used to provide a high precision programming voltage for programming memory cells having two or more analog states.

    10.
    发明专利
    未知

    公开(公告)号：DE69521882D1

    公开(公告)日：2001-08-30

    申请号：DE69521882

    申请日：1995-01-06

    Applicant: INTEL CORP

    Inventor： FAZIO ALBERT ,  ATWOOD E ,  MI Q

    IPC: G11C17/00 ,  G11C11/56 ,  G11C16/02 ,  G11C27/00

    Abstract: A method and circuitry for programming a memory cell to one of at least three amounts of charge. The amount of charge placed in the memory cell is increased by increasing the voltage level of a programming pulse applied to the memory cell.

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