Idle period report for electric power management
    1.
    发明专利
    Idle period report for electric power management 有权
    空调电力管理报告

    公开(公告)号:JP2013257886A

    公开(公告)日:2013-12-26

    申请号:JP2013147879

    申请日:2013-07-16

    CPC classification number: G06F1/3234 G06F1/3215 G06F1/3228

    Abstract: PROBLEM TO BE SOLVED: To provide a device and method for reporting an idle period for electric power management.SOLUTION: Data corresponding to an idle period of one or a plurality of downstream devices is received by reporting the idle period for electric power management, and electric power is controlled at least partially on the basis of the received data.

    Abstract translation: 要解决的问题:提供用于报告电力管理的空闲时段的装置和方法。解决方案:通过报告电力管理的空闲时段来接收与一个或多个下游设备的空闲时段相对应的数据,以及 至少部分地基于所接收的数据来控制电力。

    Idle duration reporting for power management
    2.
    发明专利
    Idle duration reporting for power management 审中-公开
    空闲时间报告电力管理

    公开(公告)号:JP2010165349A

    公开(公告)日:2010-07-29

    申请号:JP2009291091

    申请日:2009-12-22

    CPC classification number: G06F1/3234 G06F1/3215 G06F1/3228

    Abstract: PROBLEM TO BE SOLVED: To provide a method and an apparatus for reporting an idle duration for power management.
    SOLUTION: Platform control logics 120 coupled to one or a plurality of processors 110, and (one or the plurality of) processors 110 has a platform controller power management controller (PCPMC) 122 to help the improvement of power efficiency for a system 100, and manage one or a plurality of components of the system 100 to enter one of a plurality of lower power or sleep states when one or a plurality of components is reduced in activity or in idling.
    COPYRIGHT: (C)2010,JPO&INPIT

    Abstract translation: 要解决的问题:提供用于报告电源管理的空闲持续时间的方法和装置。 解决方案:耦合到一个或多个处理器110的平台控制逻辑120和(一个或多个)处理器110具有平台控制器功率管理控制器(PCPMC)122,以帮助提高系统的功率效率 并且当一个或多个组件在活动中或空闲时减少时,管理系统100的一个或多个组件进入多个较低功率或睡眠状态中的一个。 版权所有(C)2010,JPO&INPIT

    ABFLACHENDE PORTALBRÜCKE .
    3.
    发明专利

    公开(公告)号:DE112017001148T5

    公开(公告)日:2018-11-22

    申请号:DE112017001148

    申请日:2017-02-02

    Applicant: INTEL CORP

    Abstract: Eine abflachende Portalbrücke (FPB) wird bereitgestellt, um das Adressieren gemäß einem ersten Adressiersystem und einem zweiten, alternativen Adressiersystem zu unterstützen. Die FPB umfasst eine Primärseite und eine Sekundärseite, wobei die Primärseite mit einem ersten Satz von Bauteilen verbindet, der gemäß einem ersten Adressiersystem adressiert ist, und die zweite Seite mit einem zweiten Satz von Bauteilen verbindet, der gemäß einem zweiten Adressiersystem adressiert ist. Das erste Adressiersystem verwendet eine einzige Busnummer innerhalb eines Bus-/Bauteil-/Funktion (BDF)-Adressraums für jedes Bauteil in dem ersten Satz von Bauteilen, und das zweite Bus Adressiersystem verwendet eine einzige Bus-Bauteilnummer für jedes Bauteil in dem zweiten Satz von Bauteilen.

    método, aparelho e sistema para a melhora dos tempos de retomada das portas raiz e dos pontos de extremidade integrados às portas raiz

    公开(公告)号:BR102014006218A2

    公开(公告)日:2015-10-13

    申请号:BR102014006218

    申请日:2014-03-14

    Applicant: INTEL CORP

    Abstract: método, aparelho e sistema para a melhora dos tempos de retomada das portas raiz e dos pontos de extremidade integrados às portas raiz. a presente invenção refere-se a um dispositivo que é determinado para ficar em um estado de baixa energia. uma transição de um estado de baixa energia para um estado ativado é iniciada; nela um tempo mínimo de retomada, fixo, é definido para transições do estado de baixa energia para o estado ativado. um recurso do dispositivo é identificado correspondendo à transição do dispositivo de um estado de baixa energia para o estado ativo, e a transição do dispositivo de um estado de baixa energia para um o estado ativo é completada com base em pelo menos parte do recurso, de modo que a transição seja concluída antes de expirado o tempo mínimo de recuperação fixado

    VIRTUAL GENERAL-PURPOSE I/O CONTROLLER
    6.
    发明公开

    公开(公告)号:EP3123322A4

    公开(公告)日:2017-12-27

    申请号:EP15769531

    申请日:2015-03-05

    Applicant: INTEL CORP

    Abstract: Technologies for virtual general purpose I/O (GPIO) include a computing device having a virtual GPIO controller driver, a virtual GPIO controller firmware interface, and a virtual GPIO controller. The driver receives a GPIO command from an operating system of the computing device. The GPIO command specifies an operation to be performed by a GPIO pin. The driver sends the GPIO command to the firmware interface. In response to the firmware interface receiving the command, the virtual GPIO controller emulates a virtual GPIO pin to implement the GPIO command. The firmware interface may trigger an interrupt that can be received by the operating system. The virtual GPIO controller may emulate the virtual GPIO pin using firmware-reserved backing memory, an embedded controller, or an interface to a peripheral device of the computing device. The firmware interface may be an ACPI control method. Other embodiments are described and claimed.

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