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    Method for providing peripheral component interconnect (pci)-compatible transaction level protocol for system on chip (soc)
    2.
    发明专利
    Method for providing peripheral component interconnect (pci)-compatible transaction level protocol for system on chip (soc) 有权
    提供用于芯片系统（SOC）的外围元件互连（PCI）可转换交易层协议的方法

    公开(公告)号：JP2011138521A

    公开(公告)日：2011-07-14

    申请号：JP2011003534

    申请日：2011-01-12

    Applicant: Intel Corp ,  インテル コーポレイション

    Inventor： SHOEMAKER KEN ,  WAGH MAHESH ,  HAN WOOJONG ,  ATHREYA MADHU ,  MANDHANI ARVIND ,  THAKKAR SHREEKANT S

    IPC: G06F13/38

    CPC classification number: G06F13/404 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4027 ,  G06F13/4045

    Abstract: PROBLEM TO BE SOLVED: To provide a system which allows PC compatibility, in regard to PC compatibility wherein reuse of a component is limited in accordance with change in silicon process by mixing of a physical level regulated in an interface and a transaction level in a conventional system on chip (SoC) system.
    SOLUTION: The system includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is similarly coupled via one or more physical units to heterogeneous resources.
    COPYRIGHT: (C)2011,JPO&INPIT

    Abstract translation: 要解决的问题：为了提供一种允许PC兼容性的系统，关于PC兼容性，其中通过混合接口中调节的物理电平和事务级别来限制组件的重用性，这是根据硅工艺的变化而受到限制的 在传统的片上系统（SoC）系统中。 解决方案：该系统包括具有根据个人计算机（PC）协议和第二协议进行通信的适配器的装置。 耦合到适配器的第一接口是对从适配器的上游接收的事务执行地址转换和排序。 第一接口类似地通过一个或多个物理单元耦合到异构资源。 版权所有（C）2011，JPO＆INPIT

    Method for providing peripheral component interconnection (pci)-compatible transaction level protocol for system on chip (soc)
    3.
    发明专利
    Method for providing peripheral component interconnection (pci)-compatible transaction level protocol for system on chip (soc) 有权
    用于提供芯片（SOC）系统的外围元件互连（PCI）可转换交易层协议的方法

    公开(公告)号：JP2009289264A

    公开(公告)日：2009-12-10

    申请号：JP2009127455

    申请日：2009-05-27

    Applicant: Intel Corp ,  インテル コーポレイション

    Inventor： SHOEMAKER KEN ,  WAGH MAHESH ,  HAN WOOJONG ,  ATHREYA MADHU ,  MANDHANI ARVIND ,  THAKKAR SHREEKANT S

    IPC: G06F13/36 ,  G06F15/78

    CPC classification number: G06F13/404 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4027 ,  G06F13/4045

    Abstract: PROBLEM TO BE SOLVED: To provide a method for achieving PC compatibility in a system on chip (SoC) system.
    SOLUTION: In order to achieve use of a resource of a different sort such as a PCI-based system AXI/OCP technique, modular interconnection of a transaction level of a PC compatible SoC component is performed. Since the transaction level can be separated from a prescribed physical level in the specifications of the SoC component, a function for mapping a PCI (or another bus-based) system in a point-to-point (PtP) interconnection system, a function for PtP interconnecting target-based decoding, and target-based decoding in the PC compatible system and other PC compatible function are achieved through logic.
    COPYRIGHT: (C)2010,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种在片上系统（SoC）系统中实现PC兼容性的方法。 解决方案：为了实现诸如基于PCI的系统AXI / OCP技术的不同类型的资源，执行PC兼容SoC组件的事务级别的模块化互连。 由于事务级别可以与SoC组件的规范中的规定物理级别分离，所以用于在点对点（PtP）互连系统中映射PCI（或另一基于总线的）系统的功能， 通过逻辑实现了在PC兼容系统和其他PC兼容功能中的PtP互连目标解码和基于目标的解码。 版权所有（C）2010，JPO＆INPIT

    ADDRESS TRANSLATION CACHING AND I/O CACHE PERFORMANCE IMPROVEMENT IN VIRTUALIZED ENVIRONMENTS
    4.
    发明申请
    ADDRESS TRANSLATION CACHING AND I/O CACHE PERFORMANCE IMPROVEMENT IN VIRTUALIZED ENVIRONMENTS 审中-公开
    地址转换缓存和I / O缓存在虚拟化环境中的性能改进

    公开(公告)号：WO2009045884A3

    公开(公告)日：2009-06-25

    申请号：PCT/US2008077819

    申请日：2008-09-26

    Applicant: INTEL CORP ,  WAGH MAHESH ,  AJANOVIC JASMIN

    Inventor： WAGH MAHESH ,  AJANOVIC JASMIN

    IPC: G06F12/08

    CPC classification number: G06F12/08 ,  G06F12/023 ,  G06F12/10 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/121 ,  G06F2212/152

    Abstract: Methods and apparatus relating to improving address translation caching and/or input/output (I/O) cache performance in virtualized environments are described. In one embodiment, a hint provided by an endpoint device may be utilized to update information stored in an I/O cache. Such information may be utilized for implementation of a more efficient replacement policy in an embodiment. Other embodiments are also disclosed.

    Abstract translation: 描述了与在虚拟化环境中改善地址翻译缓存和/或输入/输出（I / O）缓存性能有关的方法和装置。 在一个实施例中，可以利用由端点设备提供的提示来更新存储在I / O高速缓存中的信息。 在一个实施例中，可以利用这样的信息来实现更有效的替换策略。 其他实施例也被公开。

    OPTIMIZED LINK TRAINING AND MANAGEMENT MECHANISM
    5.
    发明申请
    OPTIMIZED LINK TRAINING AND MANAGEMENT MECHANISM 审中-公开
    优化的链接培训和管理机制

    公开(公告)号：WO2013176954A3

    公开(公告)日：2014-02-27

    申请号：PCT/US2013041322

    申请日：2013-05-16

    Applicant: INTEL CORP

    Inventor： WAGH MAHESH ,  HARRIMAN DAVID J

    IPC: G06F13/42 ,  G06F1/32

    CPC classification number: G06F13/4282 ,  G06F1/3253 ,  G06F13/385 ,  H04Q2213/13003 ,  Y02B60/1235 ,  Y02B60/32 ,  Y02D10/151 ,  Y02D50/20

    Abstract: In one embodiment, a converged protocol stack can be used to unify communications from a first communication protocol to a second communication protocol to provide for data transfer across a physical interconnect. This stack can be incorporated in an apparatus that includes a protocol stack for a first communication protocol including transaction and link layers, and a physical (PHY) unit coupled to the protocol stack to provide communication between the apparatus and a device coupled to the apparatus via a physical link. This PHY unit may include a physical unit circuit according to the second communication protocol. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，可以使用融合协议栈来将通信从第一通信协议统一到第二通信协议，以提供跨物理互连的数据传输。 该堆栈可以并入包括用于包括事务和链路层的第一通信协议的协议栈的装置，以及耦合到协议栈的物理（PHY）单元，以在装置和耦合到装置的装置之间通信 一个物理链接。 该PHY单元可以包括根据第二通信协议的物理单元电路。 描述和要求保护其他实施例。

    A PACKETIZED INTERFACE FOR COUPLING AGENTS
    6.
    发明申请
    A PACKETIZED INTERFACE FOR COUPLING AGENTS 审中-公开
    用于联接代理的封装接口

    公开(公告)号：WO2010129096A3

    公开(公告)日：2011-01-13

    申请号：PCT/US2010027604

    申请日：2010-03-17

    Applicant: INTEL CORP ,  WAGH MAHESH ,  SINGHAL ABHISHEK ,  AJANOVIC JASMIN

    Inventor： WAGH MAHESH ,  SINGHAL ABHISHEK ,  AJANOVIC JASMIN

    IPC: G06F13/42

    CPC classification number: H04L69/22 ,  G06F13/385 ,  Y02B60/1228 ,  Y02B60/1235 ,  Y02D10/14 ,  Y02D10/151

    Abstract: In one embodiment, the present invention includes a fabric on a first semiconductor die to communicate with at least one agent on the die according to an on-chip protocol and a packetization layer coupled to the fabric to receive command and data information from the fabric on multiple links and to packetize the information into a packet for transmission from the die to another die via an in-package packetized link. Other embodiments are described and claimed

    Abstract translation: 在一个实施例中，本发明包括在第一半导体芯片上的结构，用于根据片上协议与芯片上的至少一个代理通信，以及耦合到该结构的分组层，以从该结构接收命令和数据信息 多个链路，并将该信息分组成一个数据包，以便通过一个封包内分组化链路从芯片传输到另一个管芯。 描述和要求保护其他实施例

    OPTIMIZED LINK TRAINING AND MANAGEMENT MECHANISM
    8.
    发明申请
    OPTIMIZED LINK TRAINING AND MANAGEMENT MECHANISM 审中-公开
    优化的链接培训与管理机制

    公开(公告)号：WO2013176954A2

    公开(公告)日：2013-11-28

    申请号：PCT/US2013041322

    申请日：2013-05-16

    Applicant: INTEL CORP

    Inventor： WAGH MAHESH ,  HARRIMAN DAVID J

    IPC: G06F13/42 ,  G06F1/32

    CPC classification number: G06F13/4282 ,  G06F1/3253 ,  G06F13/385 ,  H04Q2213/13003 ,  Y02B60/1235 ,  Y02B60/32 ,  Y02D10/151 ,  Y02D50/20

    Abstract: In one embodiment, a converged protocol stack can be used to unify communications from a first communication protocol to a second communication protocol to provide for data transfer across a physical interconnect. This stack can be incorporated in an apparatus that includes a protocol stack for a first communication protocol including transaction and link layers, and a physical (PHY) unit coupled to the protocol stack to provide communication between the apparatus and a device coupled to the apparatus via a physical link. This PHY unit may include a physical unit circuit according to the second communication protocol. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，可以使用融合协议栈来将通信从第一通信协议统一到第二通信协议，以提供跨物理互连的数据传输。 该堆叠可以并入包括用于包括交易和链路层的第一通信协议的协议栈的装置，以及耦合到协议栈的物理（PHY）单元，以在设备和耦合到装置的设备之间通信 一个物理链接。 该PHY单元可以包括根据第二通信协议的物理单元电路。 描述和要求保护其他实施例。

    ENABLING FLEXIBILITY OF PACKET LENGTH IN A COMMUNICATION PROTOCOL
    9.
    发明申请
    ENABLING FLEXIBILITY OF PACKET LENGTH IN A COMMUNICATION PROTOCOL 审中-公开
    在通信协议中实现分组长度的灵活性

    公开(公告)号：WO2009094339A2

    公开(公告)日：2009-07-30

    申请号：PCT/US2009031461

    申请日：2009-01-20

    Applicant: INTEL CORP ,  WAGH MAHESH

    Inventor： WAGH MAHESH

    IPC: G06F13/42 ,  G06F13/14 ,  H04L12/56

    CPC classification number: G06F13/385 ,  G06F13/4269 ,  H04L12/12 ,  Y02D50/30 ,  Y02D50/40

    Abstract: In one embodiment, the present invention includes a method for transmitting a packet from a transmitter to a receiver along an interconnect and terminating transmission of the packet at a packet disconnect boundary, which has a length less than a payload length of the packet. After such termination, another packet such as a higher priority packet can be transmitted, or a remainder of the original packet may be transmitted as a separate packet. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，本发明包括一种用于沿着互连从发射机向接收机发送分组并且在分组断开边界处终止发送分组的传输的方法，该分组断开边界的长度小于分组的有效载荷长度。 在这种终止之后，可以发送诸如较高优先级分组之类的另一分组，或者可以将原始分组的其余部分作为单独的分组来发送。 描述并要求保护其他实施例。

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