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    3D MEMORY CONFIGURABLE FOR PERFORMANCE AND POWER
    1.
    发明申请
    3D MEMORY CONFIGURABLE FOR PERFORMANCE AND POWER 审中-公开
    3D内存可配置性能和功耗

    公开(公告)号：WO2014051729A3

    公开(公告)日：2014-07-31

    申请号：PCT/US2013045218

    申请日：2013-06-11

    Applicant: INTEL CORP

    Inventor： SARASWAT RUCHIR ,  GRIES MATTHIAS

    IPC: G11C11/40 ,  G11C11/4074

    CPC classification number: G11C5/063 ,  G11C5/025 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4097 ,  G11C2207/2227 ,  H01L24/16 ,  H01L25/0657 ,  H01L27/0688 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541

    Abstract: A 3D memory that is configurable for performance and power. An embodiment of a memory device includes a dynamic random-access memory (DRAM) including multiple memory dies, each memory die including multiple memory arrays, each memory array including peripheral logic circuits and a configurable logic. The memory device further includes a system element coupled with the DRAM, the system element including a memory controller. The memory controller is to provide for control of the configurable logic to provide for separate or shared peripheral logic circuits for one or more memory arrays, the configurable logic being configurable to enable or disable one or more of the peripheral logic circuits and to enable or disable one or more I/O connections between the memory arrays.

    Abstract translation: 可配置性能和功耗的3D内存。 存储器件的实施例包括包括多个存储器管芯的动态随机存取存储器（DRAM），每个存储器管芯包括多个存储器阵列，每个存储器阵列包括外围逻辑电路和可配置逻辑。 存储器件还包括与DRAM耦合的系统元件，系统元件包括存储器控制器。 存储器控制器旨在提供对可配置逻辑的控制以提供用于一个或多个存储器阵列的单独或共享的外围逻辑电路，所述可配置逻辑可配置为启用或禁用外围逻辑电路中的一个或多个并启用或禁用 存储器阵列之间的一个或多个I / O连接。

    Heterogenous memory access
    2.
    发明专利
    Heterogenous memory access 未知

    公开(公告)号：GB2519641A

    公开(公告)日：2015-04-29

    申请号：GB201414980

    申请日：2014-08-22

    Applicant: INTEL CORP

    Inventor： SARASWAT RUCHIR ,  GRIES MATTHIAS ,  COWLEY NICHOLAS PAUL

    IPC: G06F3/06 ,  G06F1/32

    Abstract: A memory controller 110 operable for selective memory access to areas 150 of memory 120 exhibiting different attributes leverages different memory capabilities that vary access speed, retention time and power consumption, among others. Different areas of memory have different attributes while remaining available to applications as a single contiguous range of addressable memory. The memory controller employs an operating mode that identifies operational priorities for a computing device, such as speed, power conservation, or efficiency. The memory controller identifies an area of memory based on an expected usage of the data stored in the area, for example an access frequency indicating future retrieval. The memory controller therefore selects areas of memory based on the operating mode and the expected usage of data to be stored in the area according to a heuristic that favours areas of memory based on those exhibiting attributes having a high correspondence to the expected usage of the data.

    Heterogener Speicherzugriff
    3.
    发明专利
    Heterogener Speicherzugriff 未知

    公开(公告)号：DE102014111990A1

    公开(公告)日：2015-03-19

    申请号：DE102014111990

    申请日：2014-08-21

    Applicant: INTEL CORP

    Inventor： SARASWAT RUCHIR ,  GRIES MATTHIAS ,  COWLEY NICHOLAS P

    IPC: G11C7/00 ,  G06F11/34 ,  G06F12/02 ,  G11C11/407

    Abstract: Ein Speicher-Controller, der für den selektiven Speicherzugriff auf Speicherbereiche eingesetzt werden kann, die unterschiedliche Merkmale aufweisen, gleicht unterschiedliche Speicherkapazitäten aus, die u. a. die Zugangsgeschwindigkeit, die Retentionsdauer und den Stromverbrauch variieren. Verschiedene Speicherbereiche haben verschiedene Merkmale, sind jedoch für Anwendungen als ein einziger durchgängiger, adressierbarer Speicherbereich verfügbar. Der Speicher-Controller wendet eine Betriebsart an, die operative Prioritäten für einen Rechner erkennt, z. B. Geschwindigkeit, Energieeinsparung oder Effizienz. Der Speicher-Controller erkennt einen Speicherbereich auf Grund einer erwarteten Nutzung der in dem Bereich gespeicherten Daten, z. B. eine Zugriffshäufigkeit, die auf den zukünftigen Datenabruf hinweist. Der Speicher-Controller wählt deshalb Speicherbereiche auf Grund der Betriebsart und der erwarteten Nutzung der in dem Bereich zu speichernden Daten gemäß einer Heuristik aus, die Speicherbereiche auf der Grundlage dieser Merkmale, die der erwarteten Datennutzung am ehesten entsprechen, begünstigt.

    CACHE OPERATIONS FOR MEMORY MANAGEMENT
    4.
    发明公开
    CACHE OPERATIONS FOR MEMORY MANAGEMENT 审中-公开
    CACHESPEICHEROPERATIONEN ZUR SPEICHERVERWALTUNG

    公开(公告)号：EP3049937A4

    公开(公告)日：2017-05-17

    申请号：EP13894149

    申请日：2013-09-27

    Applicant: INTEL CORP

    Inventor： KRANICH TIM ,  GRIES MATTHIAS ,  LINKEWITSCH NIKLAS

    IPC: G06F12/08 ,  G06F12/02 ,  G06F12/12

    CPC classification number: G06F12/0891 ,  G06F9/4406 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0802 ,  G06F12/0848 ,  G06F12/0877 ,  G06F12/0893 ,  G06F12/1054 ,  G06F12/12 ,  G06F12/126 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/1032 ,  G06F2212/60 ,  G06F2212/69 ,  G06F2212/7201 ,  G06F2212/7203 ,  G06F2212/7211 ,  Y02B60/1225 ,  Y02D10/13

    Abstract: In accordance with the present description, cache operations for a memory-sided cache in front of a backing memory such as a byte-addressable non-volatile memory, include combining at least two of a first operation, a second operation and a third operation, wherein the first operation includes evicting victim cache entries from the cache memory in accordance with a replacement policy which is biased to evict cache entries having clean cache lines over evicting cache entries having dirty cache lines. The second operation includes evicting victim cache entries from the primary cache memory to a victim cache memory of the cache memory, and the third operation includes translating memory location addresses to shuffle and spread the memory location addresses within an address range of the backing memory. It is believed that various combinations of these operations may provide improved operation of a memory. Other aspects are described herein.

    Abstract translation: 根据本说明书，用于诸如字节可寻址的非易失性存储器之类的后备存储器之前的存储器侧高速缓存的高速缓存操作包括组合第一操作，第二操作和第三操作中的至少两个， 其中所述第一操作包括根据替代策略从所述高速缓存存储器中逐出受害者高速缓存条目，所述替换策略偏向于驱逐具有干净的高速缓存行的高速缓存条目，以驱逐具有脏高速缓存行的高速缓存条目。 第二操作包括将受害者高速缓存条目从主高速缓存存储器驱逐到高速缓存存储器的受害者高速缓存存储器，并且第三操作包括翻译存储器位置地址以混洗并在后备存储器的地址范围内扩展存储器位置地址。 相信这些操作的各种组合可以提供改善的存储器操作。 这里描述了其他方面。

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