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    Combining instruction including instruction that performs sequence of transformation to isolate one transformation
    1.
    发明专利
    Combining instruction including instruction that performs sequence of transformation to isolate one transformation 有权
    组合指令，包括执行转换顺序以隔离一次转换的指令

    公开(公告)号：JP2009211071A

    公开(公告)日：2009-09-17

    申请号：JP2009045094

    申请日：2009-02-27

    Applicant: Intel Corp ,  インテル コーポレイション

    Inventor： GUERON SHAY ,  SPERBER ZEEV

    IPC: G09C1/00

    CPC classification number: H04L9/0681 ,  G06F9/30007 ,  G06F21/75 ,  G06F2221/2107 ,  G09C1/00 ,  H04L9/0631 ,  H04L2209/125 ,  H04L2209/24

    Abstract: PROBLEM TO BE SOLVED: To provide the Advanced Encryption Standard (AES) that is a symmetric block cipher capable of encrypting and decrypting information. SOLUTION: Encryption (cipher) performs a series of transformations (Shift Rows, Substitute Bytes, Mix Columns) using a secret key (cipher key) to transform intelligible data referred to as "plaintext" into an unintelligible form referred to as "cipher text". The transformations (Inverse Shift Rows, Inverse Substitute Bytes, Inverse Mix Columns) in the inverse cipher (decryption) are the inverse of the transformations in the cipher. Encryption and decryption is performed efficiently through the use of instructions that perform the series of transformations. Combinations of these instructions allow the isolation of the transformations (Shift Rows, Substitute Bytes, Mix Columns, Inverse Shift Rows, Inverse Substitute Bytes, Inverse Mix Columns) to be obtained. COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题：提供能够加密和解密信息的对称块密码的高级加密标准（AES）。 解决方案：加密（密码）使用秘密密钥（密码密钥）执行一系列转换（Shift Rows，Substitute Bytes，Mix Columns），将可被称为“明文”的可理解数据转换为一种不可理解的形式，称为“ 密文“。 反密码（解密）中的变换（逆位排，逆替换字节，反混合列）是密码中的变换的逆。 通过使用执行一系列转换的指令来有效地执行加密和解密。 这些指令的组合允许要获得的转换的隔离（Shift Rows，Substitution Bytes，Mix Columns，Inverse Shift Rows，Inverse Substitute Bytes，Inverse Mix Columns）。 版权所有（C）2009，JPO＆INPIT

    Method and apparatus for optimizing advanced encryption standard (aes) encryption and decryption in parallel mode of operation
    2.
    发明专利
    Method and apparatus for optimizing advanced encryption standard (aes) encryption and decryption in parallel mode of operation 有权
    用于优化并行运行模式下的高级加密标准（AES）加密和分解的方法和装置

    公开(公告)号：JP2009205161A

    公开(公告)日：2009-09-10

    申请号：JP2009043695

    申请日：2009-02-26

    Applicant: Intel Corp ,  インテル コーポレイション

    Inventor： GUERON SHAY ,  GRADSTEIN AMIT ,  SPERBER ZEEV

    IPC: G09C1/00

    CPC classification number: H04L9/0631 ,  G06F9/30007 ,  H04L2209/125

    Abstract: PROBLEM TO BE SOLVED: To optimize advanced encryption standard (AES) encryption and decryption in parallel modes of operation.
    SOLUTION: The throughput of an encryption/decryption operation is increased in a system having a pipelined execution unit. Different independent encryptions (decryptions) of different data blocks may be performed in parallel by despatching an AES round instruction in each cycle.
    COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题：以并行运行模式优化先进的加密标准（AES）加密和解密。 解决方案：在具有流水线执行单元的系统中，加密/解密操作的吞吐量增加。 可以通过在每个周期中发送AES循环指令来并行地执行不同数据块的不同的独立加密（解密）。 版权所有（C）2009，JPO＆INPIT

    Device, system, and method for solving simultaneous linear equation using parallel processing
    4.
    发明专利
    Device, system, and method for solving simultaneous linear equation using parallel processing 有权
    使用并行处理解决同时线性方程的装置，系统和方法

    公开(公告)号：JP2009266230A

    公开(公告)日：2009-11-12

    申请号：JP2009104914

    申请日：2009-04-23

    Applicant: Intel Corp ,  インテル コーポレイション

    Inventor： MYASKOUVSKEY ARTIOM ,  GUERON SHAY

    IPC: G06F17/12 ,  H04N7/01

    CPC classification number: G06F17/12 ,  H04N5/145 ,  H04N7/0127

    Abstract: PROBLEM TO BE SOLVED: To efficiently solve simultaneous linear equations that may be used to estimate motion between frames in a video file for converting frame rates. SOLUTION: A method includes the steps for: multiplying a matrix which is a representation of large and sparse simultaneous linear equations, which is used to estimate motion between frames of a video file, by a vector which is a first vector estimation of a solution to the simultaneous linear equations and has a plurality of elements arranged in a certain order; generating a second vector estimation which is a solution to the simultaneous linear equations and is a product of the multiplying; and setting the solution to the simultaneous linear equations when the first and second vector estimations differ by less than a predetermined amount, wherein the matrix is multiplied by the respective elements of the vector in an order different from the order in which the elements are arranged in the vector, wherein the plurality of elements in the vector are multiplied in parallel. COPYRIGHT: (C)2010,JPO&INPIT

    Abstract translation: 要解决的问题：有效地解决可用于估计用于转换帧速率的视频文件中的帧之间的运动的同时线性方程式。 解决方案：一种方法包括以下步骤：乘以作为用于估计视频文件的帧之间的运动的大的和稀疏的联立线性方程式的表示的矩阵，该矢量是作为第一矢量估计的矢量 对于联立线性方程组的解决方案，并且具有以特定顺序排列的多个元件; 产生第二向量估计，其是对联立线性方程的解，并且是乘法的乘积; 以及当所述第一和第二矢量估计值相差小于预定量时将所述解决方案设置为所述同时线性方程式，其中所述矩阵以与所述元素排列的顺序不同的顺序与所述向量的各个元素相乘 矢量，其中矢量中的多个元素并行相乘。 版权所有（C）2010，JPO＆INPIT

    Performing aes encryption or decryption in multiple modes with single instruction
    5.
    发明专利
    Performing aes encryption or decryption in multiple modes with single instruction 有权
    在单个指令的多种模式下执行AES加密或解码

    公开(公告)号：JP2008283672A

    公开(公告)日：2008-11-20

    申请号：JP2008064272

    申请日：2008-03-13

    Applicant: Intel Corp ,  インテル コーポレイション

    Inventor： DIXON MARTIN ,  CHENNUPATY SRINIVAS ,  GUERON SHAY

    IPC: H04L9/10 ,  G06F9/30 ,  G09C1/00

    CPC classification number: H04L9/0631 ,  G06F9/30007 ,  H04L9/0637 ,  H04L9/28 ,  H04L2209/12

    Abstract: PROBLEM TO BE SOLVED: To provide an Advanced Encryption Standard (AES) encryption instruction, having two operands, encrypting/decrypting data in at least two modes. SOLUTION: The present invention relates to a machine-readable medium which may have stored thereon an instruction, which, when executed by a machine, causes the machine to perform a method. The method may include combining a first operand of the instruction and a second operand of the instruction to produce a result. The result may be encrypted using a key in accordance with an Advanced Encryption Standard (AES) algorithm to produce an encrypted result. The method may also include placing the encrypted result in a location of the first operand of the instruction. COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题：提供具有两个操作数的高级加密标准（AES）加密指令，以至少两种模式对数据进行加密/解密。 解决方案：本发明涉及一种机器可读介质，其可以存储有指令，当由机器执行时，该指令使机器执行方法。 该方法可以包括组合指令的第一操作数和指令的第二操作数以产生结果。 可以使用根据高级加密标准（AES）算法的密钥来加密结果以产生加密结果。 该方法还可以包括将加密结果放置在指令的第一操作数的位置。 版权所有（C）2009，JPO＆INPIT

    A TWEAKABLE ENCRYPION MODE FOR MEMORY ENCRYPTION WITH PROTECTION AGAINST REPLAY ATTACKS
    6.
    发明申请
    A TWEAKABLE ENCRYPION MODE FOR MEMORY ENCRYPTION WITH PROTECTION AGAINST REPLAY ATTACKS 审中-公开
    内存加密与防止重击攻击的双重加密模式

    公开(公告)号：WO2012040679A3

    公开(公告)日：2012-07-19

    申请号：PCT/US2011053170

    申请日：2011-09-24

    Applicant: INTEL CORP ,  GUERON SHAY ,  GERZON GIDEON ,  ANATI ITTAI ,  DOWECK JACOB ,  MAOR MOSHE

    Inventor： GUERON SHAY ,  GERZON GIDEON ,  ANATI ITTAI ,  DOWECK JACOB ,  MAOR MOSHE

    IPC: G06F21/20 ,  G06F12/14

    CPC classification number: G06F12/1408 ,  G06F21/52 ,  G06F21/64

    Abstract: A method and apparatus for protecting against hardware attacks on system memory is provided. A mode of operation for block ciphers enhances the standard XTS-AES mode of operation to perform memory encryption by extending a tweak to include a "time stamp" indicator. An incrementing mechanism using the "time stamp" indicator generates a tweak which separates different contexts over different times such that the effect of "Type 2 replay attacks" is mitigated.

    Abstract translation: 提供了一种用于防止对系统存储器的硬件​​攻击的方法和装置。 分组密码的操作模式增强了标准的XTS-AES操作模式，通过扩展调整以包括“时间戳”指示符来执行存储器加密。 使用“时间戳”指示符的递增机制产生了在不同时间分离不同上下文的调整，使得“类型2重放攻击”的效果得到缓解。

    DETERMINING A MESSAGE RESIDUE
    7.
    发明申请
    DETERMINING A MESSAGE RESIDUE 审中-公开
    确定消息剩余

    公开(公告)号：WO2009012050A2

    公开(公告)日：2009-01-22

    申请号：PCT/US2008068801

    申请日：2008-06-30

    Applicant: INTEL CORP ,  GUERON SHAY ,  GOPAL VINODH ,  FEGHALI WAJDI K ,  WOLRICH GILBERT

    Inventor： GUERON SHAY ,  GOPAL VINODH ,  FEGHALI WAJDI K ,  WOLRICH GILBERT

    IPC: G06F7/52

    CPC classification number: H03M13/091

    Abstract: A technique of determining a message residue includes accessing a message and simultaneously determining a set of modular remainders with respect to a polynomial for different respective segments of the message. The technique also includes determining a modular remainder with respect to the polynomial for the message based on the set of modular remainders and a set of constants determined prior to accessing the message. The modular remainder with respect to the polynomial for the message is stored in a memory.

    Abstract translation: 确定消息余数的技术包括访问消息并同时针对消息的不同相应段针对多项式确定一组模块余数。 该技术还包括基于在访问消息之前确定的一组模块余数和一组常量来确定关于消息的多项式的模余数。 关于消息多项式的模余数存储在存储器中。

    MEASURING A SECURE ENCLAVE
    10.
    发明公开
    MEASURING A SECURE ENCLAVE 有权
    MESSUNG EINER SICHEREN ENKLAVE

    公开(公告)号：EP3025266A4

    公开(公告)日：2017-03-01

    申请号：EP14829313

    申请日：2014-07-15

    Applicant: INTEL CORP

    Inventor： ROZAS CARLOS V ,  ANATI ITTAI ,  GERZON GIDEON ,  GUERON SHAY ,  JOHNSON SIMON P ,  MCKEEN FRANCIS X ,  SAVAGAONKAR UDAY R ,  SCARLATA VINCENT R

    IPC: G06F21/00 ,  G06F9/06

    CPC classification number: H04L9/3239 ,  G06F12/1441 ,  G06F21/71 ,  G06F2221/2111

    Abstract: Embodiments of an invention for measuring a secure enclave are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive a first, a second, and a third instruction. The execution unit is to execute the first, the second, and the third instruction. Execution of the first instruction includes initializing a measurement field in a control structure of a secure enclave with an initial value. Execution of the second instruction includes adding a region to the secure enclave. Execution of the third instruction includes measuring a subregion of the region.

    Abstract translation: 公开了用于测量安全飞地的发明的实施例。 在一个实施例中，处理器包括指令单元和执行单元。 指令单元将接收第一，第二和第三指令。 执行单元执行第一条，第二条和第三条指令。 第一指令的执行包括用初始值初始化安全区域的控制结构中的测量字段。 第二条指令的执行包括向安全飞地增加一个区域。 第三条指令的执行包括测量该地区的一个子地区。

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