公开(公告)号：JP2011146077A

公开(公告)日：2011-07-28

申请号：JP2011101385

申请日：2011-04-28

Applicant: Intel Corp ,  インテル コーポレイション

Inventor： WANG HONG ,  SHEN JOHN ,  ZHANG HONG ,  HANKINS RICHARD ,  HAMMARLUND PER ,  RODGERS DION ,  CHINYA GAUTHAM ,  PATEL BAIJU ,  KAUSHIK SHIV ,  BIGBEE BRYANT ,  SHEAFFER GAD ,  TALGAM YOAV ,  YOSEF YUVAL ,  HELD JAMES P

IPC: G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/30 ,  G06F9/30181 ,  G06F9/3877 ,  G06F9/3879 ,  G06T1/20

Abstract: PROBLEM TO BE SOLVED: To provide a method, a device, and a system for performing effective communication between instruction set architecture-based sequencers having heterogeneous resources. SOLUTION: The method includes: a step in which a first instruction sequencer is connected from a user-level application via the first instruction sequencer and a request is directly communicated to an accelerator having a heterogeneous resource with respect to the instruction sequencer; a step of providing the accelerator with the request via an exoskeleton related to the accelerator; and a step of performing a first function in parallel to a second function in the first instruction sequencer in response to the request in the accelerator. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于在具有异构资源的指令集体系结构的定序器之间执行有效通信的方法，设备和系统。 该方法包括：第一指令定序器经由第一指令定序器从用户级应用连接并且请求直接传送到相对于指令定序器具有异构资源的加速器的步骤; 通过与加速器有关的外骨骼提供加速器请求的步骤; 以及响应于加速器中的请求，在第一指令定序器中执行与第二功能并行的第一功能的步骤。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2007183943A

公开(公告)日：2007-07-19

申请号：JP2006348294

申请日：2006-12-25

Applicant: Intel Corp ,  インテル コーポレイション

Inventor： WANG HONG ,  SHEN JOHN ,  ZHANG HONG ,  HANKINS RICHARD ,  HAMMARLUND PER ,  RODGERS DION ,  CHINYA GAUTHAM ,  PATEL BAIJU ,  KAUSHIK SHIV ,  BIGBEE BRYANT ,  SHEAFFER GAD ,  TALGAM YOAV ,  YOSEF YUVAL ,  HELD JAMES P

IPC: G06F9/38 ,  G06F9/50

CPC classification number: G06F9/30145 ,  G06F9/30 ,  G06F9/30181 ,  G06F9/3877 ,  G06F9/3879 ,  G06T1/20

Abstract: PROBLEM TO BE SOLVED: To provide a method, a device, and a system allowing effective communication between respective instruction set architecture base sequencers having heterogeneous resources. SOLUTION: This method is constructed of steps for: directly transmitting a request to an accelerator, which is connected via a first instruction sequencer and has heterogeneous resources about the first instruction sequencer, from a user level application to the first instruction sequencer; offering the request to the accelerator via an exoskeleton about the accelerator; and executing a first function in the accelerator in response to the request in parallel to a second function in the first instruction sequencer. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种允许具有异构资源的各个指令集架构基本定序器之间有效通信的方法，设备和系统。 解决方案：该方法由以下步骤构成：用于通过第一指令定序器将与第一指令定序器相关的异构资源从用户级应用程序直接传送到加速器的请求到第一指令定序器; 通过关于加速器的外骨骼向加速器提出要求; 以及响应于与第一指令定序器中的第二功能并行的请求，在加速器中执行第一功能。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2014059920A

公开(公告)日：2014-04-03

申请号：JP2014000371

申请日：2014-01-06

Applicant: Intel Corp ,  インテル コーポレイション

Inventor： WANG HONG ,  SHEN JOHN ,  ZHANG HONG ,  HANKINS RICHARD ,  HAMMARLUND PER ,  DION ROGERS ,  CHINYA GAUTHAM ,  PATEL BAIJU ,  KAUSHIK SHIV ,  BIGBEE BRYANT ,  SHEAFFER GAD ,  TALGAM YOAV ,  YOSEF YUVAL ,  HELD JAMES P

IPC: G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/30 ,  G06F9/30181 ,  G06F9/3877 ,  G06F9/3879 ,  G06T1/20

Abstract: PROBLEM TO BE SOLVED: To provide a method, apparatus, system that enables effective communication between instruction set architecture-based sequencers having heterogeneous resources.SOLUTION: The method comprises: directly communicating a request from a user-level application to an accelerator coupled to a first instruction sequencer via the first instruction sequencer, where the accelerator comprises a heterogeneous resource with respect to the first instruction sequencer; providing the request to the accelerator via an exo-skeleton associated with the accelerator; and performing a first function in the accelerator in response to the request in parallel with a second function in the first instruction sequencer.

Abstract translation: 要解决的问题：提供一种使得能够在具有异构资源的指令集体系结构的定序器之间有效通信的方法，装置，系统。解决方案：该方法包括：将来自用户级应用的请求直接传达到耦合到 所述第一指令定序器经由所述第一指令定序器，其中所述加速器包括相对于所述第一指令定序器的异质资源; 通过与加速器相关联的外部骨架向加速器提供请求; 以及响应于与第一指令定序器中的第二功能并行的请求在加速器中执行第一功能。

公开(公告)号：JP2013254524A

公开(公告)日：2013-12-19

申请号：JP2013195581

申请日：2013-09-20

Applicant: INTEL CORP

Inventor： CHINYA GAUTHAM N ,  HAUN WARNE ,  MATHAIKUTTY DEEPAK A ,  COLLINS JAMISON D ,  SCHUCHMAN ETHAN ,  HELD JAMES P ,  BHATT AJAY V ,  SETHI PRASHANT ,  WHALLEY STEPHEN F

IPC: G06F12/10 ,  G06F12/08

Abstract: PROBLEM TO BE SOLVED: To provide hardware support for virtual memory shared between local physical memory and remote physical memory.SOLUTION: A method comprises: receiving a memory access request including a virtual address; analyzing an entry corresponding to the virtual address stored in a translation lookaside buffer (TLB) of a processor in order to determine if a physical address (PA) corresponding to the virtual address is present in a local memory associated with the processor or a remote memory associated with an accelerator coupled to the processor via a non-coherent link; and if the PA is present in the remote memory, sending a reverse proxy execution request to the remote memory in order to perform the memory access request. The local memory and the remote memory collectively form a shared virtual memory space.

公开(公告)号：JP2011065650A

公开(公告)日：2011-03-31

申请号：JP2010205550

申请日：2010-09-14

Applicant: Intel Corp ,  インテル コーポレイション

Inventor： CHINYA GAUTHAM N ,  WANG HONG ,  MATHAIKUTTY DEEPAK A ,  COLLINS JAMISON D ,  SCHUCHMAN ETHAN ,  HELD JAMES P ,  BHATT AJAY V ,  SETHI PRASHANT ,  WHALLEY STEPHEN F

IPC: G06F12/10 ,  G06F12/02 ,  G06F12/06 ,  G06F12/08

CPC classification number: G06F12/1036 ,  G06F12/1027 ,  G06F12/121 ,  G06F2212/254

Abstract: PROBLEM TO BE SOLVED: To provide hardware support for a virtual memory shared between a local physical memory and a remote physical memory.
SOLUTION: A method includes the steps of: receiving a memory access request including a virtual address; analyzing an entry corresponding to the virtual address stored in a conversion look-aside buffer (TLB) of a processor, in order to determine whether a physical address (PA) corresponding to the virtual address exists in the remote memory attached to an accelerator connected to the processor, via the local memory or a non-coherent link attached to the processor; and transmitting a reverse proxy execution request to the remote memory, in order to execute the memory access request, when the PA exists in the remote memory. The local memory and the remote memory constitute a common virtual memory space.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：为本地物理内存和远程物理内存之间共享的虚拟内存提供硬件支持。 解决方案：一种方法包括以下步骤：接收包括虚拟地址的存储器访问请求; 分析与存储在处理器的转换后备缓冲器（TLB）中的虚拟地址相对应的条目，以便确定与连接到加速器的加速器相连的远程存储器中是否存在与虚拟地址相对应的物理地址（PA） 处理器，经由本地存储器或连接到处理器的非相干链路; 并且当远程存储器中存在PA时，为了执行存储器访问请求，向远程存储器发送反向代理执行请求。 本地内存和远程内存构成了一个通用的虚拟内存空间。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：BRPI1003466A2

公开(公告)日：2015-08-18

申请号：BRPI1003466

申请日：2010-09-16

Applicant: INTEL CORP

Inventor： CHINYA GAUTHAM N ,  WANG HONG ,  MATHAIKUTTY DEEPAK A ,  COLLINS JAMISON D ,  SCHUCHMAN ETHAN ,  HELD JAMES P ,  BHATT AJAY V ,  SETHI PRASHANT ,  WHALLEY STEPHEN F

IPC: G06F12/10

Abstract: Método, dispositivo e sistema de suporte de hardware para o compartilhamento de memória virtual entre memória física local e remota. Em uma realização, a presente invenção inclui uma unidade de gerenciamento de memória (mmu) que possui entradas para armazenar endereços virtuais para conversões de endereços físicos, em que cada entrada inclui um indicador de local para indicar se um local de memória para a entrada correspondente está presente em uma memória local ou remota. Dessa maneira, um espaço de memória virtual comum pode ser compartilhado entre as duas memórias, que podem ser separadas por um ou mais links não coerentes. Outras realizações são descritas e reivindicadas

公开(公告)号：DE102010035603A1

公开(公告)日：2011-04-07

申请号：DE102010035603

申请日：2010-08-27

Applicant: INTEL CORP

Inventor： CHINYA GAUTHAM N ,  SCHUCHMAN ETHAN ,  WANG HONG ,  HELD JAMES P ,  MATHAIKUTTY DEEPAK A ,  BHATT AJAY V ,  COLLINS JAMISON D ,  SETHI PRASHANT ,  WHALLEY STEPHEN F

IPC: G06F12/10 ,  G06F9/30 ,  G06F12/08 ,  G06F13/00

公开(公告)号：EP2729896A4

公开(公告)日：2015-04-22

申请号：EP12807077

申请日：2012-07-05

Applicant: INTEL CORP

Inventor： HELD JAMES P ,  ROBINSON SCOTT H ,  ZIMMER VINCENT J

IPC: G06F21/57 ,  G06F21/64

CPC classification number: G06F21/575 ,  G06F9/4401 ,  G06F21/64

Abstract: A system and method for BIOS flash attack protection and notification. A processor initialization module, including initialization firmware verification module may be configured to execute first in response to a power on and/or reset and to verify initialization firmware stored in non-volatile memory in a processor package. The initialization firmware is configured to verify the BIOS. If the verification of the initialization firmware and/or the BIOS fails, the system is configured to select at least one of a plurality of responses including, but not limited to, preventing the BIOS from executing, initiating recovery, reporting the verification failure, halting, shutting down and/or allowing the BIOS to execute and an operating system (OS) to boot in a limited functionality mode.