公开(公告)号：GB2190521A

公开(公告)日：1987-11-18

申请号：GB8628175

申请日：1986-11-25

Applicant: INTEL CORP

Inventor： MYERS GLENFORD J ,  LAI KONRAD ,  IMEL MICHAEL T ,  HINTON GLENN ,  RICHES ROBERT

IPC: G06F9/42 ,  G06F9/30 ,  G06F9/40 ,  G06F9/46 ,  G06F12/08

Abstract: A plurality of global registers are provided on the microprocessor chip. One of a global registers is a frame pointer register containing the current frame pointer, and the remainder of the global registers are available to a current process as general registers. A plurality of floating point registers are also provided for use by the current process in execution of floating point arithmetic operations. A register set pool made up of a plurality of register sets is provided, each register set being comprised of a number of local registers. When a call instruction is decoded, a register set of local registers from the register set pool is allocated to the called procedure, and the frame pointer register is initialized. When a return instruction is decoded, the register set is freed for allocation to another procedure called by a subsequent call instruction. If the register set pool is depleted a register set associated with a previous procedure is saved in the main memory, and that register set is allocated to the current procedure. The local registers in a register set associated with a procedure contain linkage information including a pointer to the previous frame and an instruction pointer, thus enabling most call and return instructions to execute without needing any references to off-chip memory.

公开(公告)号：GB2192507B

公开(公告)日：1990-05-09

申请号：GB8703090

申请日：1987-02-11

Applicant: INTEL CORP

Inventor： IMEL MICHAEL T

IPC: G11C15/04

Abstract: A content addressable memory including a pair of column lines (54, 56) upon which information to be matched with the contents of said memory is placed. The memory is driven by a clock such that during particular clock phase a ROW line (50) and a MATCH line (52) are precharged and both column lines are discharged. The memory cell is comprised of transistors (M1, M2, M3, M4) connected to each other and to a supply voltage (Vcc) to thereby form a cross-coupled inverter storage device. Transistors (M5, M6) are connected to diode transistor (M7) and between the cross-coupled inverter (M1, M2, M3, M4) and column lines (54, 56) to thereby form and XOR gate on said column lines (54, 56) and diode transistor (M7). The diode transistor is connected between transistors (M5, M6), ROW line (50) and MATCH line (52), such that during CAM matches the diode transistor allows charge to be siphoned from MATCH line ( 52) and during a write to said CAM cell allows charge to build up.

公开(公告)号：FR2598835A1

公开(公告)日：1987-11-20

申请号：FR8618432

申请日：1986-12-31

Applicant: INTEL CORP

Inventor： MYERS GLENFORD J ,  LAI KONRAD ,  IMEL MICHAEL T ,  HINTON GLENN ,  RICHES ROBERT

IPC: G06F9/42 ,  G06F9/30 ,  G06F9/40 ,  G06F9/46 ,  G06F12/08 ,  G06F12/00

Abstract: A plurality of global registers are provided on the microprocessor chip. One of a global registers is a frame pointer register containing the current frame pointer, and the remainder of the global registers are available to a current process as general registers. A plurality of floating point registers are also provided for use by the current process in execution of floating point arithmetic operations. A register set pool made up of a plurality of register sets is provided, each register set being comprised of a number of local registers. When a call instruction is decoded, a register set of local registers from the register set pool is allocated to the called procedure, and the frame pointer register is initialized. When a return instruction is decoded, the register set is freed for allocation to another procedure called by a subsequent call instruction. If the register set pool is depleted a register set associated with a previous procedure is saved in the main memory, and that register set is allocated to the current procedure. The local registers in a register set associated with a procedure contain linkage information including a pointer to the previous frame and an instruction pointer, thus enabling most call and return instructions to execute without needing any references to off-chip memory.

公开(公告)号：DE3716229A1

公开(公告)日：1987-11-19

申请号：DE3716229

申请日：1987-05-14

Applicant: INTEL CORP

Inventor： MEYERS GLENFORD J ,  LAI KONRAD ,  IMEL MICHAEL T ,  HINTON GLENN ,  RICHES ROBERT

IPC: G06F9/42 ,  G06F9/30 ,  G06F9/40 ,  G06F9/46 ,  G06F12/08 ,  G06F9/34

Abstract: A plurality of global registers are provided on the microprocessor chip. One of a global registers is a frame pointer register containing the current frame pointer, and the remainder of the global registers are available to a current process as general registers. A plurality of floating point registers are also provided for use by the current process in execution of floating point arithmetic operations. A register set pool made up of a plurality of register sets is provided, each register set being comprised of a number of local registers. When a call instruction is decoded, a register set of local registers from the register set pool is allocated to the called procedure, and the frame pointer register is initialized. When a return instruction is decoded, the register set is freed for allocation to another procedure called by a subsequent call instruction. If the register set pool is depleted a register set associated with a previous procedure is saved in the main memory, and that register set is allocated to the current procedure. The local registers in a register set associated with a procedure contain linkage information including a pointer to the previous frame and an instruction pointer, thus enabling most call and return instructions to execute without needing any references to off-chip memory.

公开(公告)号：DE3716229C2

公开(公告)日：1996-08-14

申请号：DE3716229

申请日：1987-05-14

Applicant: INTEL CORP

Inventor： MEYERS GLENFORD J ,  LAI KONRAD ,  IMEL MICHAEL T ,  HINTON GLENN ,  RICHES ROBERT

IPC: G06F9/42 ,  G06F9/30 ,  G06F9/40 ,  G06F9/46 ,  G06F12/08 ,  G06F9/34

Abstract: A plurality of global registers are provided on the microprocessor chip. One of a global registers is a frame pointer register containing the current frame pointer, and the remainder of the global registers are available to a current process as general registers. A plurality of floating point registers are also provided for use by the current process in execution of floating point arithmetic operations. A register set pool made up of a plurality of register sets is provided, each register set being comprised of a number of local registers. When a call instruction is decoded, a register set of local registers from the register set pool is allocated to the called procedure, and the frame pointer register is initialized. When a return instruction is decoded, the register set is freed for allocation to another procedure called by a subsequent call instruction. If the register set pool is depleted a register set associated with a previous procedure is saved in the main memory, and that register set is allocated to the current procedure. The local registers in a register set associated with a procedure contain linkage information including a pointer to the previous frame and an instruction pointer, thus enabling most call and return instructions to execute without needing any references to off-chip memory.

公开(公告)号：GB2190521B

公开(公告)日：1990-01-10

申请号：GB8628175

申请日：1986-11-25

Applicant: INTEL CORP

Inventor： MYERS GLENFORD J ,  LAI KONRAD ,  IMEL MICHAEL T ,  HINTON GLENN ,  RICHES ROBERT

IPC: G06F9/42 ,  G06F9/30 ,  G06F9/40 ,  G06F9/46 ,  G06F12/08

Abstract: A plurality of global registers are provided on the microprocessor chip. One of a global registers is a frame pointer register containing the current frame pointer, and the remainder of the global registers are available to a current process as general registers. A plurality of floating point registers are also provided for use by the current process in execution of floating point arithmetic operations. A register set pool made up of a plurality of register sets is provided, each register set being comprised of a number of local registers. When a call instruction is decoded, a register set of local registers from the register set pool is allocated to the called procedure, and the frame pointer register is initialized. When a return instruction is decoded, the register set is freed for allocation to another procedure called by a subsequent call instruction. If the register set pool is depleted a register set associated with a previous procedure is saved in the main memory, and that register set is allocated to the current procedure. The local registers in a register set associated with a procedure contain linkage information including a pointer to the previous frame and an instruction pointer, thus enabling most call and return instructions to execute without needing any references to off-chip memory.

公开(公告)号：FR2598835B1

公开(公告)日：1993-09-03

申请号：FR8618432

申请日：1986-12-31

Applicant: INTEL CORP

Inventor： MYERS GLENFORD J ,  LAI KONRAD ,  IMEL MICHAEL T ,  HINTON GLENN ,  RICHES ROBERT

IPC: G06F9/42 ,  G06F9/30 ,  G06F9/40 ,  G06F9/46 ,  G06F12/08 ,  G06F12/00

Abstract: A plurality of global registers are provided on the microprocessor chip. One of a global registers is a frame pointer register containing the current frame pointer, and the remainder of the global registers are available to a current process as general registers. A plurality of floating point registers are also provided for use by the current process in execution of floating point arithmetic operations. A register set pool made up of a plurality of register sets is provided, each register set being comprised of a number of local registers. When a call instruction is decoded, a register set of local registers from the register set pool is allocated to the called procedure, and the frame pointer register is initialized. When a return instruction is decoded, the register set is freed for allocation to another procedure called by a subsequent call instruction. If the register set pool is depleted a register set associated with a previous procedure is saved in the main memory, and that register set is allocated to the current procedure. The local registers in a register set associated with a procedure contain linkage information including a pointer to the previous frame and an instruction pointer, thus enabling most call and return instructions to execute without needing any references to off-chip memory.

公开(公告)号：GB2192507A

公开(公告)日：1988-01-13

申请号：GB8703090

申请日：1987-02-11

Applicant: INTEL CORP

Inventor： IMEL MICHAEL T

IPC: G11C15/04

Abstract: A content addressable memory including a pair of column lines (54, 56) upon which information to be matched with the contents of said memory is placed. The memory is driven by a clock such that during particular clock phase a ROW line (50) and a MATCH line (52) are precharged and both column lines are discharged. The memory cell is comprised of transistors (M1, M2, M3, M4) connected to each other and to a supply voltage (Vcc) to thereby form a cross-coupled inverter storage device. Transistors (M5, M6) are connected to diode transistor (M7) and between the cross-coupled inverter (M1, M2, M3, M4) and column lines (54, 56) to thereby form and XOR gate on said column lines (54, 56) and diode transistor (M7). The diode transistor is connected between transistors (M5, M6), ROW line (50) and MATCH line (52), such that during CAM matches the diode transistor allows charge to be siphoned from MATCH line ( 52) and during a write to said CAM cell allows charge to build up.