公开(公告)号：EP3055882A4

公开(公告)日：2018-02-14

申请号：EP14891614

申请日：2014-12-22

Applicant: INTEL CORP

Inventor： JEN WEI-LUN KANE ,  JAIN PADAM ,  SENEVIRATNE DILAN ,  CHEN CHI-MON

IPC: H01L25/065 ,  H05K1/03 ,  H05K1/11 ,  H05K3/00

CPC classification number: H05K1/0271 ,  H01L21/02002 ,  H01L21/02008 ,  H01L21/02035 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/12 ,  H01L23/13 ,  H01L23/3185 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/16 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/0002 ,  H01L2924/15311 ,  H05K1/0298 ,  H05K1/036 ,  H05K1/0393 ,  H05K1/115 ,  H05K1/181 ,  H05K3/0014 ,  H05K3/0044 ,  H05K2201/0191 ,  H05K2201/05 ,  H05K2203/0278 ,  H05K2203/085 ,  H01L2924/00

Abstract: Embodiments disclosed include a multilayer substrate for semiconductor packaging. The substrate may include a first layer with a first side with an xy-plane and individual locations on the first side have a first side distance below the first side xy-plane, and a second side with a second side xy-plane and individual locations on the second side may have a second side distance below the second side xy-plane; and a second layer with a first side coupled to the second side of the first layer and a second side opposite the first side of the second layer, wherein a thickness of the second layer at the individual locations on the second layer may be comprised of the first side distance plus the second side distance. Other embodiments may be described and/or claimed.