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    COMMON IDLE STATE, ACTIVE STATE AND CREDIT MANAGEMENT FOR AN INTERFACE
    1.
    发明申请
    COMMON IDLE STATE, ACTIVE STATE AND CREDIT MANAGEMENT FOR AN INTERFACE 审中-公开
    通用空闲状态，接口状态和信用管理

    公开(公告)号：WO2013048856A2

    公开(公告)日：2013-04-04

    申请号：PCT/US2012056255

    申请日：2012-09-20

    Applicant: INTEL CORP

    Inventor： LAKSHMANAMURTHY SRIDHAR ,  ADLER ROBERT P ,  HUNSAKER MIKAL C ,  KLINGLESMITH MICHAEL T ,  FANNING BLAISE ,  TAMARI ERAN ,  MURRAY JOSEPH ,  VERMA ROHIT R

    CPC classification number: G06F13/42 ,  G06F9/466 ,  G06F15/7825 ,  G06F15/7864 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

    Abstract: In one embodiment, the present invention includes method for entering a credit initialization state of an agent state machine of an agent coupled to a fabric to initialize credits in a transaction credit tracker of the fabric. This tracker tracks credits for transaction queues of a first channel of the agent for a given transaction type. The agent may then assert a credit initialization signal to cause credits to be stored in the transaction credit tracker corresponding to the number of the transaction queues of the first channel of the agent for the first transaction type. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，本发明包括用于输入耦合到结构的代理的代理状态机的信用初始化状态以便初始化该结构的交易信用跟踪器中的信用的方法。 该跟踪器跟踪给定交易类型的代理的第一渠道的交易队列的信用。 然后，代理可以断言信用初始化信号，以使得信用被存储在与第一交易类型的代理的第一渠道的交易队列的数量相对应的交易信用跟踪器中。 描述和要求保护其他实施例。

    3.
    发明专利
    未知

    公开(公告)号：DE112006002565T5

    公开(公告)日：2008-08-14

    申请号：DE112006002565

    申请日：2006-09-26

    Applicant: INTEL CORP

    Inventor： LAKSHMANAMURTHY SRIDHAR ,  ROSENBLUTH MARK

    IPC: G06F12/12 ,  G06F12/08

    Abstract: Instruction-assisted cache management for efficient use of cache and memory. Hints (e.g., modifiers) are added to read and write memory access instructions to identify the memory access is for temporal data. In view of such hints, alternative cache policy and allocation policies are implemented that minimize cache and memory access. Under one policy, a write cache miss may result in a write of data to a partial cache line without a memory read/write cycle to fill the remainder of the line. Under another policy, a read cache miss may result in a read from memory without allocating or writing the read data to a cache line. A cache line soft-lock mechanism is also disclosed, wherein cache lines may be selectably soft locked to indicate preference for keeping those cache lines over non-locked lines.

    5.
    发明专利
    未知

    公开(公告)号：DE112006002912T5

    公开(公告)日：2009-06-18

    申请号：DE112006002912

    申请日：2006-12-11

    Applicant: INTEL CORP

    Inventor： LAKSHMANAMURTHY SRIDHAR ,  WILKINSON HUGH M III ,  SYDIR JAROSLAW J ,  DORMITZIR PAUL

    IPC: H04L12/56

    Abstract: Methods and apparatus, including computer program products, implementing techniques for monitoring a state of a device of a switched fabric network, the device including on-chip queues to store queue descriptors and a data buffer to store data packets, each queue descriptor having a corresponding data packet; detecting a first trigger condition to transition the device from a first state to a second state; and recovering space in the data buffer in response to the first trigger condition detecting, the recovering comprising selecting one or more of the on-chip queues for discard, and removing the data packets corresponding to queue descriptors in the selected one or more on-chip queues from the data buffer.

    7.
    发明专利
    未知

    公开(公告)号：AT490628T

    公开(公告)日：2010-12-15

    申请号：AT05732332

    申请日：2005-03-31

    Applicant: INTEL CORP

    Inventor： KUMAR ALOK ,  KOUNAVIS MICHAEL ,  YAVATKAR RAJ ,  CHANDRA PRASHANT ,  LAKSHMANAMURTHY SRIDHAR ,  KUO CHEN-CHI ,  VIN HARRICK

    IPC: H04L12/56 ,  H04L29/06

    Abstract: A method and apparatus for two-stage packet classification. In the first stage, which may be implemented in software, a packet is classified on the basis of the packet's network path and, perhaps, its protocol. In the second stage, which may be implemented in hardware, the packet is classified on the basis of one or more transport level fields of the packet. An apparatus of two-stage packet classification may include a processing system for first stage code execution, a classification circuit for performing the second stage of classification, and a memory to store a number of bins, each bin including one or more rules.

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