公开(公告)号：EP3230878A4

公开(公告)日：2018-07-25

申请号：EP15867831

申请日：2015-11-13

Applicant: INTEL CORP

Inventor： WU KEQIANG ,  LU JIWEI ,  LEE YONG-FONG

IPC: G06F13/16 ,  G06F8/52 ,  G06F8/70 ,  G06F9/30 ,  G06F11/30 ,  G06F11/34 ,  G06F13/14

CPC classification number: G06F9/30065 ,  G06F8/52 ,  G06F8/70 ,  G06F9/30087 ,  G06F11/3024 ,  G06F11/3409 ,  G06F11/3466 ,  G06F2201/81 ,  G06F2201/825 ,  G06F2201/865 ,  G06F2201/88

Abstract: One embodiment provides an apparatus. The apparatus includes a processor, a chipset, a memory to store a process, and logic. The processor includes one or more core(s) and is to execute the process. The logic is to acquire performance monitoring data in response to a platform processor utilization parameter (PUP) greater than a detection utilization threshold (UT), identify a spin loop based, at least in part, on at least one of a detected hot function and/or a detected hot loop, modify the identified spin loop using binary translation to create a modified process portion, and implement redirection from the identified spin loop to the modified process portion.

公开(公告)号：EP3234844A4

公开(公告)日：2018-08-01

申请号：EP15870567

申请日：2015-11-16

Applicant: INTEL CORP

Inventor： YAMADA KOICHI ,  BIJLANI ASHISH ,  LU JIWEI ,  ZHAO CHENG YAN

IPC: G06F8/52 ,  G06F9/30

CPC classification number: G06F9/3806 ,  G06F8/52 ,  G06F9/30054 ,  G06F9/30145

Abstract: A method is described. The method includes receiving an instruction, accessing a return cache to load a predicted return target address upon determining that the instruction is a return instruction, searching a lookup table for executable binary code upon determining that the predicted translated return target address is incorrect and executing the executable binary code to perform a binary translation.

公开(公告)号：EP3014423A4

公开(公告)日：2017-03-15

申请号：EP13887955

申请日：2013-06-28

Applicant: INTEL CORP

Inventor： SARKAR ABHIK ,  LU JIWEI ,  SHANMUGAVELAYUTHAM PALANIVELRAJAN RAJAN ,  AGRON JASON M ,  YAMADA KOICHI

IPC: G06F9/455 ,  G06F9/445 ,  G06F9/48 ,  G06F9/50 ,  G06F12/02 ,  G06F12/0802

CPC classification number: G06F9/5038 ,  G06F8/61 ,  G06F8/62 ,  G06F9/45516 ,  G06F9/485 ,  G06F9/5016 ,  G06F12/0253 ,  G06F12/0802 ,  G06F2212/1044 ,  G06F2212/60

Abstract: Technologies for partial binary translation on multi-core platforms include a shared translation cache, a binary translation thread scheduler, a global installation thread, and a local translation thread and analysis thread for each processor core. On detection of a hotspot, the thread scheduler first resumes the global thread if suspended, next activates the global thread if a translation cache operation is pending, and last schedules local translation or analysis threads for execution. Translation cache operations are centralized in the global thread and decoupled from analysis and translation. The thread scheduler may execute in a non-preemptive nucleus, and the translation and analysis threads may execute in a preemptive runtime. The global thread may be primarily preemptive with a small non-preemptive nucleus to commit updates to the shared translation cache. The global thread may migrate to any of the processor cores. Forward progress is guaranteed. Other embodiments are described and claimed.

Abstract translation: 用于多核平台上部分二进制转换的技术包括共享转换缓存，二进制转换线程调度程序，全局安装线程以及每个处理器内核的本地转换线程和分析线程。 在检测到热点时，线程调度程序首先在挂起时恢复全局线程，接下来如果转换缓存操作正在等待，则激活全局线程，最后计划本地转换或分析线程执行。 翻译缓存操作集中在全局线程中，并与分析和翻译分离。 线程调度器可以在非优先级核中执行，并且转换和分析线程可以在抢占式运行时间内执行。 全局线程可能主要采用小型非抢占核来提交更新到共享转换缓存。 全局线程可能迁移到任何处理器内核。 前进进度得到保证。 描述和要求保护其他实施例。