公开(公告)号：GB2512727B

公开(公告)日：2015-10-21

申请号：GB201402938

申请日：2014-02-19

Applicant: INTEL CORP

Inventor： BOBBA JAYARAM ,  SASANKA RUCHIRA ,  COOK JEFFREY J ,  DAS ABHINAV ,  KRISHNASWAMY ARVIND ,  SAGER DAVID J ,  AGRON JASON M

IPC: G06F9/30 ,  G06F1/32 ,  G06F9/455 ,  G06F11/34 ,  G06F11/36

公开(公告)号：WO2017112361A3

公开(公告)日：2017-07-27

申请号：PCT/US2016063890

申请日：2016-11-28

Applicant: INTEL CORP

Inventor： MEKKAT VINEETH ,  MARGULIS OLEG ,  AGRON JASON M ,  SCHUCHMAN ETHAN ,  WINKEL SEBASTIAN ,  WU YOUFENG ,  DANKEL GISLE

IPC: G06F9/30 ,  G06F9/38 ,  G06F11/00 ,  G06F11/07

CPC classification number: G06F9/30185 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3865

Abstract: Embodiments of apparatus and methods for detecting and recovering from incorrect memory dependence speculation in an out-of-order processor are described herein. For example, one embodiment of a method comprises: executing a first load instruction; detecting when the first load instruction experiences a bad store-to-load forwarding event during execution; tracking the occurrences of bad store-to-load forwarding event experienced by the first load instruction during execution; controlling enablement of an S-bit in the first load instruction based on the tracked occurrences; generating a plurality of load operations responsive to an enabled S-bit in first load instruction, wherein execution of the plurality of load operations produces a result equivalent to that from the execution of the first load instruction.

Abstract translation: 这里描述了用于在无序处理器中检测并从不正确的存储器依赖性推测中恢复的设备和方法的实施例。 例如，方法的一个实施例包括：执行第一加载指令; 检测何时第一加载指令在执行期间经历了不良的存储 - 加载转发事件; 跟踪在执行期间由第一加载指令经历的不良存储 - 加载转发事件的发生; 基于所跟踪的事件来控制所述第一加载指令中的S位的启用; 响应于第一加载指令中的启用的S位产生多个加载操作，其中所述多个加载操作的执行产生与来自所述第一加载指令的执行的结果相等的结果。

公开(公告)号：GB2512727A

公开(公告)日：2014-10-08

申请号：GB201402938

申请日：2014-02-19

Applicant: INTEL CORP

Inventor： BOBBA JAYARAM ,  SASANKA RUCHIRA ,  COOK JEFFREY J ,  DAS ABHINAV ,  KRISHNASWAMY ARVIND ,  SAGER DAVID J ,  AGRON JASON M

IPC: G06F9/30 ,  G06F1/32 ,  G06F9/455 ,  G06F11/34 ,  G06F11/36

Abstract: A method of operating a device with a processor that includes receiving control flow data, the control flow data including block identifiers for blocks of instructions, destination identifiers for one or more of the blocks of the instructions, and annotations for the blocks of instructions; the method further includes determining a destination identifier for a current instruction block based on the control flow data; identifying an annotation associated with the current instruction block based on the control flow data; and performing at least one of: modifying resources used by a processor; or tracking execution of the blocks of instructions based on one or more of the annotation or the destination identifier. Optimisation of a processing device may be performed according to the annotations by way of reducing the number of components used. Tracking of the execution of the blocks of instructions may be used to determine if a hard error in memory or a soft error in execution has occurred with reference to annotation indicating the number of instructions within in a current instruction block.

公开(公告)号：DE102014003689A1

公开(公告)日：2014-09-18

申请号：DE102014003689

申请日：2014-03-14

Applicant: INTEL CORP

Inventor： AGRON JASON M ,  SASANKA RUCHIRA ,  KRISHNASWAMY ARVIND ,  COOK JEFFREY J ,  SAGER DAVID J ,  BOBBA JAYARAM ,  DAS ABHINAV

IPC: G06F9/38

Abstract: Ein Mechanismus für die Verfolgung des Kontrollflusses in einer Anwendung und die Durchführung von einer oder mehreren Optimierungen eines Verarbeitungsgeräts auf Basis des Kontrollflusses der Befehle in der Anwendung wird offenbart. Kontrollflussdaten werden erzeugt, um den Kontrollfluss der Befehlsblöcke in der Anwendung anzugeben. Die Kontrollflussdaten können Anmerkungen beinhalten, die angeben, ob Optimierungen für die verschiedenen Befehlsblöcke durchgeführt werden können. Die Kontrollflussdaten können auch verwendet werden, um die Ausführung der Befehle zu verfolgen, um zu bestimmen, ob ein Befehl in einem Befehlsblock einem Thread, einem Prozess und/oder einem Ausführungskern eines Prozessors zugewiesen ist, und um zu bestimmen, ob Fehler während der Ausführung der Befehle aufgetreten sind.

公开(公告)号：DE102018002525A1

公开(公告)日：2018-10-04

申请号：DE102018002525

申请日：2018-03-27

Applicant: INTEL CORP

Inventor： MEKKAT VINEETH ,  AGRON JASON M ,  WU YOUFENG

IPC: G06F9/38

Abstract: Eine Verarbeitungsvorrichtung, die umfasst: ein erstes Schattenregister, ein zweites Schattenregister und eine Befehlsausführungsschaltung, die kommunikationstechnisch mit dem ersten Schattenregister und dem zweiten Schattenregister gekoppelt ist und zu Folgendem ausgelegt ist: Empfangen einer Sequenz von Befehlen, die einen ersten lokalen Festschreibungsmerker, einen ersten globalen Festschreibungsmerker und einen ersten Registerzugriffsbefehl, der auf ein Architekturregister verweist, umfasst, spekulatives Ausführen des ersten Registerzugriffsbefehls, um einen spekulativen Registerzustandswert zu erzeugen, der einem physischen Register zugeordnet ist, als Antwort auf das Identifizieren der ersten lokalen Festschreibungsmerkers, Speichern des spekulativen Registerzustandswerts in dem ersten Schattenregister, und, als Antwort auf das Identifizieren des ersten globalen Festschreibungsmerkers, Speichern des spekulativen Registerzustandswerts in dem zweiten Schattenregister.

公开(公告)号：BR102014005801A2

公开(公告)日：2016-03-15

申请号：BR102014005801

申请日：2014-03-13

Applicant: INTEL CORP

Inventor： DAS ABHINAV ,  KRISHNASWAMY ARVIND ,  SAGER DAVID J ,  AGRON JASON M ,  BORBA JAYARAM ,  COOK JEFFREY J ,  SASANKA RUCHIRA

IPC: G06F9/30 ,  G06F9/44 ,  G06F11/00

Abstract: rastreamento de fluxo de controle de instruções - um mecanismo para rastrear o fluxo de controle de instruções em uma aplicação e realizar uma ou mais otimizações de um dispositivo de processamento, com base no fluxo de controle de instruções na aplicação, é revelado. os dados de fluxo de controle são gerados para indicar o fluxo de controle de blocos de instruções na aplicação. os dados de fluxo de controle podem incluir anotações que indicam se otimizações pode ser realizadas para diferentes blocos de instruções. os dados de fluxo de controle podem também ser usados para rastrear a execução das instruções para determinar se uma instrução em um bloco de instruções está atribuída a um thread, um processo, e/ou um núcleo de execução de um processador, e para determinar se os erros ocorreram durante a execução das instruções.

公开(公告)号：EP2972826A4

公开(公告)日：2016-10-19

申请号：EP13877577

申请日：2013-03-13

Applicant: INTEL CORP

Inventor： AGRON JASON M ,  YAMADA KOICHI

IPC: G06F9/45

CPC classification number: G06F9/5027 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/329 ,  G06F9/505 ,  G06F9/5094 ,  G06F2209/5017 ,  Y02D10/22 ,  Y02D10/24

Abstract: Embodiments of techniques and systems associated with binary translation (BT) in computing systems are disclosed. In some embodiments, a BT task to be processed may be identified. The BT task may be associated with a set of code and may be identified during execution of the set of code on a first processing core of the computing device. The BT task may be queued in a queue accessible to a second processing core of the computing device, the second processing core being different from the first processing core. In response to a determination that the second processing core is in an idle state or has received an instruction through an operating system to enter an idle state, at least some of the BT task may be processed using the second processing core. Other embodiments may be described and/or claimed.

Abstract translation: 公开了与计算系统中的二进制翻译（BT）相关联的技术和系统的实施例。 在一些实施例中，可以识别要处理的BT任务。 BT任务可以与一组代码相关联，并且可以在计算设备的第一处理核心处的该代码集的执行期间被识别。 BT任务可以排队在计算设备的第二处理核心可访问的队列中，第二处理核心与第一处理核心不同。 响应于确定第二处理核心处于空闲状态或已经通过操作系统接收到进入空闲状态的指令，可以使用第二处理核来处理至少一些BT任务。 可以描述和/或要求保护其他实施例。

公开(公告)号：EP3014423A4

公开(公告)日：2017-03-15

申请号：EP13887955

申请日：2013-06-28

Applicant: INTEL CORP

Inventor： SARKAR ABHIK ,  LU JIWEI ,  SHANMUGAVELAYUTHAM PALANIVELRAJAN RAJAN ,  AGRON JASON M ,  YAMADA KOICHI

IPC: G06F9/455 ,  G06F9/445 ,  G06F9/48 ,  G06F9/50 ,  G06F12/02 ,  G06F12/0802

CPC classification number: G06F9/5038 ,  G06F8/61 ,  G06F8/62 ,  G06F9/45516 ,  G06F9/485 ,  G06F9/5016 ,  G06F12/0253 ,  G06F12/0802 ,  G06F2212/1044 ,  G06F2212/60

Abstract: Technologies for partial binary translation on multi-core platforms include a shared translation cache, a binary translation thread scheduler, a global installation thread, and a local translation thread and analysis thread for each processor core. On detection of a hotspot, the thread scheduler first resumes the global thread if suspended, next activates the global thread if a translation cache operation is pending, and last schedules local translation or analysis threads for execution. Translation cache operations are centralized in the global thread and decoupled from analysis and translation. The thread scheduler may execute in a non-preemptive nucleus, and the translation and analysis threads may execute in a preemptive runtime. The global thread may be primarily preemptive with a small non-preemptive nucleus to commit updates to the shared translation cache. The global thread may migrate to any of the processor cores. Forward progress is guaranteed. Other embodiments are described and claimed.

Abstract translation: 用于多核平台上部分二进制转换的技术包括共享转换缓存，二进制转换线程调度程序，全局安装线程以及每个处理器内核的本地转换线程和分析线程。 在检测到热点时，线程调度程序首先在挂起时恢复全局线程，接下来如果转换缓存操作正在等待，则激活全局线程，最后计划本地转换或分析线程执行。 翻译缓存操作集中在全局线程中，并与分析和翻译分离。 线程调度器可以在非优先级核中执行，并且转换和分析线程可以在抢占式运行时间内执行。 全局线程可能主要采用小型非抢占核来提交更新到共享转换缓存。 全局线程可能迁移到任何处理器内核。 前进进度得到保证。 描述和要求保护其他实施例。