公开(公告)号：JP2006092575A

公开(公告)日：2006-04-06

申请号：JP2005343925

申请日：2005-11-29

Applicant: Intel Corp ,  インテル・コーポレーション

Inventor： SARANGDHAR NITIN V ,  LAI KONRAD K ,  SINGH GURBIR ,  MACWILLIAMS PETER D

IPC: G06F13/36 ,  G06F13/42 ,  G06F13/368 ,  G06F13/37

CPC classification number: G06F13/37 ,  G06F13/368 ,  G06F13/4213

Abstract: PROBLEM TO BE SOLVED: To provide a method and device for executing a random-order response in a pipelined bus system. SOLUTION: In executing a bus transaction on a bus of a computer system, the random-order response is performed including transmission (302) of a token between a requesting-side agent and a responding-side agent within the computer system, without using an exclusive token bus. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于在流水线总线系统中执行随机顺序响应的方法和装置。 解决方案：在计算机系统的总线执行总线事务时，执行随机顺序响应，包括在计算机系统内的请求方代理和响应方代理之间的令牌的传输（302） 而不使用专用令牌总线。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：US6412060B2

公开(公告)日：2002-06-25

申请号：US77736201

申请日：2001-02-05

Applicant: INTEL CORP

Inventor： MACWILLIAMS PETER D ,  PAWLOWSKI STEPHEN S

IPC: G06F12/02 ,  G06F11/10 ,  G06F12/06 ,  G06F13/42 ,  G06F12/00

CPC classification number: G06F11/1016 ,  G06F12/0623

Abstract: A method and apparatus for supporting multiple overlapping address spaces on a shared bus includes both an address comparator and an address size indicator. The address comparator compares an address, corresponding to a request to be issued on the bus, to a plurality of address spaces. The address size indicator indicates a first address space of the plurality of address spaces to which the address corresponds.

Abstract translation: 用于在共享总线上支持多个重叠地址空间的方法和装置包括地址比较器和地址大小指示符。 地址比较器将对应于总线上要发出的请求的地址与多个地址空间进行比较。 地址大小指示符指示地址对应的多个地址空间的第一地址空间。

公开(公告)号：WO9832063A3

公开(公告)日：1999-03-18

申请号：PCT/US9722147

申请日：1997-12-03

Applicant: INTEL CORP

Inventor： JAYAKUMAR MUTHURAJAN ,  HUANG SUNNY C ,  MACWILLIAMS PETER D ,  WU WILLIAM S ,  PAWLOWSKI STEPHEN ,  PRASAD BINDI A

IPC: G06F13/37 ,  G06F13/42 ,  G06F

CPC classification number: G06F13/37 ,  G06F13/4252

Abstract: A split transaction bus in a computer system that permits out-of-order replies in a pipelined manner using an additional bus for use in the response phase.

公开(公告)号：WO0038064A9

公开(公告)日：2000-12-07

申请号：PCT/US9930170

申请日：1999-12-22

Applicant: INTEL CORP

Inventor： HOLMAN THOMAS J ,  MACWILLIAMS PETER D

IPC: G06F11/10

CPC classification number: G06F11/1028 ,  G06F11/1036

Abstract: A method and apparatus for detecting errors in data output from memory and a device failure in the memory. In the invention, a check code is generated based on data to be input to the memory. The check code is valid when equal to zero. The check code is inverted and input along with the data as a codeword to the memory in response to a write command. The codeword is output from the memory in response to a read command. The codeword output from memory indicates whether a device in memory has failed. The inverted check code included in the codeword output from memory is re-inverted. Information indicating whether the data included in the codeword output from memory includes an error is generated based on the data and the codeword including the check code.

Abstract translation: 一种用于检测从存储器输出的数据中的错误和存储器中的设备故障的方法和装置。 在本发明中，基于要输入到存储器的数据生成校验码。 检查码在等于零​​时有效。 响应于写命令，校验码被反转并作为代码字与数据一起输入存储器。 响应于读取命令，从存储器输出码字。 从存储器输出的码字指示存储器中的设备是否失败。 包括在从存储器输出的码字中的反转检查码被重新反转。 指示基于包括校验码的数据和码字来生成包括在从存储器输出的码字中包括的数据是否包含错误的信息。

公开(公告)号：EP1032880A4

公开(公告)日：2002-03-27

申请号：EP98932898

申请日：1998-06-25

Applicant: INTEL CORP

Inventor： PAWLOWSKI STEPHEN S ,  MACWILLIAMS PETER D ,  WU WILLIAM S ,  SCHULTZ LEN J

IPC: G06F13/38 ,  G06F13/40 ,  G06F13/00

CPC classification number: G06F13/385 ,  G06F13/4018 ,  G06F13/405

Abstract: A method and apparatus for transferring data between bus (101) agents in a computer system (100) including a bus operating at a bus (101) clock rate. The method includes the step of receiving a transaction request from a requesting agent including an indication of a plurality of data widths the requesting agent processes. In response to the transation request, a data transmission is configured in accordance with a data width that both the requesting agent and a responding agent process. The data transmission is performed asynchronously with respect to the bus (101) clock if the data width is one of a first plurality of data widths, otherwise, the data transmission is performed synchronously with respect to the bus clock.

公开(公告)号：EP1046111A4

公开(公告)日：2002-01-23

申请号：EP99900759

申请日：1999-01-05

Applicant: INTEL CORP

Inventor： MACWILLIAMS PETER D ,  WU WILLIAM S ,  SAMPATH DILIP K ,  PRASAD BINDI A

IPC: G06F13/42 ,  G06F13/38 ,  G06F13/40

CPC classification number: G06F13/385 ,  G06F13/4018 ,  G06F13/405

Abstract: A method and apparatus for transferring data between bus agents (102-105) in a computer system (100). The present invention includes transmitting a control signal (428, 426), from a first agent (102-105) to a second agent (102-105), via a first transfer protocol; and transmitting data (308) corresponding to the control signal (428, 426), from the first agent (102-105) to the second agent (102-105), via a second transfer protocol. In one embodiment, the control signals (428, 426) are transmitted from the first agent (102-105) to the second agent (102-105) via a synchronous transmission with respect to a bus clock (600); and, the data is transmitted via an asynchronous transmission with respect to the bus clock (600). The synchronous transmission is a common clock data transfer protocol, and the asynchronous transmission is a source clock data transfer protocol.

公开(公告)号：HK1023194A1

公开(公告)日：2000-09-01

申请号：HK00101946

申请日：2000-03-29

Applicant: INTEL CORP

Inventor： WU WILLIAM ,  PAWLOWSKI STEPHEN S ,  MACWILLIAMS PETER D

IPC: G06F12/10 ,  G06F

Abstract: Prior art methods of maintaining coherency among multiple TLBs in a multiprocessor system were time-consuming. One microprocessor halted all other microprocessors in the system, and sent an interrupt to each of the halted microprocessors. Rather than invoking an interrupt handler, the TLB shootdown operation of the present invention provides for a TLB flush transaction communicated between multiple processors on a host bus. One microprocessor issues a TLB flush request on the host bus. The TLB flush request includes a page number. The microprocessors receiving the request invalidate the TLB entry corresponding to the page number.

公开(公告)号：AU8268498A

公开(公告)日：1999-01-04

申请号：AU8268498

申请日：1998-06-25

Applicant: INTEL CORP

Inventor： PAWLOWSKI STEPHEN S ,  MACWILLIAMS PETER D ,  WU WILLIAM S ,  SCHULTZ LEN J

IPC: G06F13/38 ,  G06F13/40 ,  G06F13/00

Abstract: A method and apparatus for transferring data between bus agents in a computer system including a bus operating at a bus clock rate. The method includes the step of receiving a transaction request from a requesting agent including an indication of a plurality of data widths the requesting agent processes. In response to the transaction request, a data transmission is configured in accordance with a data width that both the requesting agent and a responding agent process. The data transmission is performed asynchronously with respect to the bus clock if the data width is one of a first plurality of data widths, otherwise, the data transmission is performed synchronously with respect to the bus clock.

公开(公告)号：AU5687898A

公开(公告)日：1998-07-15

申请号：AU5687898

申请日：1997-12-01

Applicant: INTEL CORP

Inventor： WU WILLIAM S ,  PAWLOWSKI STEPHEN S ,  MACWILLIAMS PETER D

IPC: G06F12/10 ,  G06F13/14

Abstract: Prior art methods of maintaining coherency among multiple TLBs in a multiprocessor system were time-consuming. One microprocessor halted all other microprocessors in the system, and sent an interrupt to each of the halted microprocessors. Rather than invoking an interrupt handler, the TLB shootdown operation of the present invention provides for a TLB flush transaction communicated between multiple processors on a host bus. One microprocessor issues a TLB flush request on the host bus. The TLB flush request includes a page number. The microprocessors receiving the request invalidate the TLB entry corresponding to the page number.

公开(公告)号：AU3820297A

公开(公告)日：1998-04-24

申请号：AU3820297

申请日：1997-07-28

Applicant: INTEL CORP

Inventor： PAWLOWSKI STEPHEN S ,  MACWILLIAMS PETER D ,  SINGH GURBIR

IPC: G06F13/40 ,  G06F13/00

Abstract: In a method and apparatus for changing data transfer widths in a computer system, a first agent on a bus provides a first indication to a second agent on the bus identifying one or more data transfer widths supported by the first agent. The second agent then provides a second indication to the first agent identifying one or more data transfer widths supported by the second agent. A data transfer width is then determined based on the first indication and the second indication. According to an embodiment of the present invention, a third agent involved in a transaction is also able to provide a third indication to the first and/or second agents identifying one or more data transfer widths supported by the third agent. The data transfer width(s) is then determined based on the first, second, and third indications.