公开(公告)号：JP2012109598A

公开(公告)日：2012-06-07

申请号：JP2012011073

申请日：2012-01-23

Applicant: INTEL CORP

Inventor： MARK DOGSY ,  KAVALIEROS JACK ,  MATTHEW METZ ,  JUSTIN BLASK ,  DATTA SAMANT ,  CHOU ROBERT

IPC: H01L27/092 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device.SOLUTION: A CMOS semiconductor device comprises: a high-k gate dielectric with a theoretical metal:oxygen stoichiometry; an NMOS metal gate electrode containing an aluminide with a composition represented by MAl, where M is a transition metal, disposed on the high-k gate dielectric; and a PMOS metal gate electrode not containing an aluminide disposed on the high-k gate dielectric.

公开(公告)号：NL2029298B1

公开(公告)日：2022-09-23

申请号：NL2029298

申请日：2021-09-30

Applicant: INTEL CORP

Inventor： MATTHEW METZ ,  CARL NAYLOR ,  TRISTAN TRONIC ,  ELIJAH KARPOV ,  MANISH CHANDHOK ,  NORIYUKI SATO ,  NAFEES KABIR ,  RAMANAN CHEBIAM ,  MIRIAM RESHOTKO ,  HUI JAE YOO ,  MICHAEL CHRISTENSON ,  JEFFERY BIELEFELD ,  CHRISTOPHER JEZEWSKI ,  JAMES M BLACKWELL ,  JIUN-RUEY CHEN ,  KEVIN LIN

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.

公开(公告)号：NL2029298A

公开(公告)日：2022-06-17

申请号：NL2029298

申请日：2021-09-30

Applicant: INTEL CORP

Inventor： MATTHEW METZ ,  CARL NAYLOR ,  TRISTAN TRONIC ,  ELIJAH KARPOV ,  MANISH CHANDHOK ,  NORIYUKI SATO ,  MIRIAM RESHOTOKO ,  NAFEES KABIR ,  RAMANAN CHEBIAM ,  HUI JAE YOO ,  MICHAEL CHRISTENSON ,  JEFFERY BIELEFELD ,  CHRISTOPHER JEZEWSKI ,  JAMES M BLACKWELL ,  JIUN-RUEY CHEN ,  KEVIN LIN

IPC: H01L21/768

Abstract: IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.