公开(公告)号：JP2009182360A

公开(公告)日：2009-08-13

申请号：JP2009122283

申请日：2009-05-20

Applicant: Intel Corp ,  インテル コーポレイション

Inventor： CHAU ROBERT ,  DOYLE BRIAN ,  KAVALIEROS JACK ,  BARLAGE DOUGLAS ,  DATTA SUMAN

IPC: H01L29/786 ,  H01L21/336 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/785 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/772 ,  H01L29/7854 ,  H01L29/78645 ,  H01L29/78696 ,  H01L51/0048 ,  H01L51/0554 ,  Y10S977/742 ,  Y10S977/842 ,  Y10S977/938

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device comprising a semiconductor body having a top surface sidewalls on both right and left sides formed on a substrate, and its fabrication method.
SOLUTION: A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls on both right and left sides of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and is formed adjacently to the gate dielectric on the sidewalls on both the right and left sides of the semiconductor body.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 解决的问题：提供一种半导体器件及其制造方法，该半导体器件包括在基板上形成的左右两侧具有顶面侧壁的半导体本体。 解决方案：在半导体主体的顶表面和半导体主体的左右两侧的侧壁上形成栅介质层。 栅电极形成在半导体本体的顶表面上的栅电介质上，并且与半导体本体的左右两侧的侧壁上的栅电介质相邻地形成。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2014131085A

公开(公告)日：2014-07-10

申请号：JP2014080409

申请日：2014-04-09

Applicant: Intel Corp ,  インテル コーポレイション

Inventor： CHAU ROBERT ,  DOYLE BRIAN ,  KAVALIEROS JACK ,  BARLAGE DOUGLAS ,  DATTA SUMAN

IPC: H01L29/786 ,  H01L21/336 ,  H01L29/41 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L29/785 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/772 ,  H01L29/7854 ,  H01L29/78645 ,  H01L29/78696 ,  H01L51/0048 ,  H01L51/0554 ,  Y10S977/742 ,  Y10S977/842 ,  Y10S977/938

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device comprising a semiconductor body having a top surface and sidewalls on both right and left sides formed on a substrate, and to provide a method for manufacturing the same.SOLUTION: A gate dielectric layer is formed on a top surface of a semiconductor body and on sidewalls on both right and left sides of the semiconductor body. A gate electrode is formed on a gate dielectric on the top surface of the semiconductor body and is formed adjacently to the gate dielectric on the sidewalls on both the right and left sides of the semiconductor body.

Abstract translation: 要解决的问题：提供一种半导体器件，其包括半导体本体，该半导体本体具有形成在衬底上的左右两侧的顶表面和侧壁，并提供其制造方法。解决方案：栅介质层形成在 半导体本体的顶表面和半导体本体的左右两侧的侧壁。 栅电极形成在半导体本体的顶表面上的栅极电介质上，并且与半导体本体的左右两侧的侧壁上的栅极电介质相邻地形成。

公开(公告)号：JP2012109598A

公开(公告)日：2012-06-07

申请号：JP2012011073

申请日：2012-01-23

Applicant: INTEL CORP

Inventor： MARK DOGSY ,  KAVALIEROS JACK ,  MATTHEW METZ ,  JUSTIN BLASK ,  DATTA SAMANT ,  CHOU ROBERT

IPC: H01L27/092 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device.SOLUTION: A CMOS semiconductor device comprises: a high-k gate dielectric with a theoretical metal:oxygen stoichiometry; an NMOS metal gate electrode containing an aluminide with a composition represented by MAl, where M is a transition metal, disposed on the high-k gate dielectric; and a PMOS metal gate electrode not containing an aluminide disposed on the high-k gate dielectric.

公开(公告)号：WO2010078054A2

公开(公告)日：2010-07-08

申请号：PCT/US2009068550

申请日：2009-12-17

Applicant: INTEL CORP ,  GOEL NITI ,  TSAI WILMAN ,  KAVALIEROS JACK

Inventor： GOEL NITI ,  TSAI WILMAN ,  KAVALIEROS JACK

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7391 ,  H01L29/205 ,  H01L29/66356

Abstract: A TFET includes a source region (110, 210), a drain region (120, 220), a channel region (130, 230) between the source region and the drain region, and a gate region (140, 240) adjacent to the channel region. The source region contains a first compound semiconductor including a first Group III material and a first Group V material, and the channel region contains a second compound semiconductor including a second Group III material and a second Group V material. The drain region may contain a third compound semiconductor including a third Group III material and a third Group V material.

Abstract translation: TFET包括在源极区域和漏极区域之间的源极区域（110,210），漏极区域（120,220），沟道区域（130,230）以及与该区域相邻的栅极区域（140,240） 通道区域。 源区包含第一化合物半导体，该第一化合物半导体包括第一III族材料和第一V族材料，并且沟道区包含第二化合物半导体，该第二化合物半导体包括第二III族材料和第二V族材料。 漏极区域可以包含包含第三III族材料和第三V族材料的第三化合物半导体。

公开(公告)号：WO2009042981A3

公开(公告)日：2009-06-04

申请号：PCT/US2008078041

申请日：2008-09-28

Applicant: INTEL CORP ,  JIN BEEN-YIH ,  DOYLE BRIAN ,  KAVALIEROS JACK ,  DATTA SUMAN

Inventor： JIN BEEN-YIH ,  DOYLE BRIAN ,  KAVALIEROS JACK ,  DATTA SUMAN

IPC: H01L29/78 ,  H01L29/00 ,  H01L29/80

CPC classification number: H01L29/7851 ,  H01L29/66795 ,  H01L29/7848

Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods may include providing a gate electrode comprising a top surface and first and second laterally opposite sidewalls, wherein a hard mask is disposed on the top surface, a source drain region disposed on opposite sides of the gate electrode, and a spacer disposed on the first and second laterally opposed sidewalls of the gate electrode, forming a silicon germanium layer on exposed portions of the top surface and the first and second laterally opposite sidewalls of the source drain region and then oxidizing a portion of the silicon germanium layer, wherein a germanium portion of the silicon germanium layer is forced down into the source drain region to convert a silicon portion of the source drain region into a silicon germanium portion of the source drain region.

Abstract translation: 描述形成微电子结构的方法。 这些方法的实施例可以包括提供包括顶表面和第一和第二横向相对的侧壁的栅电极，其中硬掩模设置在顶表面上，源极漏极区域设置在栅电极的相对侧上， 在栅电极的第一和第二横向相对的侧壁上，在源漏区的顶表面和第一和第二横向相对的侧壁的暴露部分上形成硅锗层，然后氧化硅锗层的一部分，其中 硅锗层的锗部分被迫下降到源极漏极区域中，以将源极区域的硅部分转换成源极漏极区域的硅锗部分。

公开(公告)号：WO2006028577A2

公开(公告)日：2006-03-16

申请号：PCT/US2005025337

申请日：2005-07-15

Applicant: INTEL CORP ,  METZ MATTHEW ,  DATTA SUMAN ,  KAVALIEROS JACK ,  DOCZY MARK ,  BRASK JUSTIN ,  CHAU ROBERT

Inventor： METZ MATTHEW ,  DATTA SUMAN ,  KAVALIEROS JACK ,  DOCZY MARK ,  BRASK JUSTIN ,  CHAU ROBERT

IPC: H01L21/8238

CPC classification number: H01L21/823462 ,  H01L21/823857

Abstract: Complementary metal oxide semiconductor integrated circuits may be formed with NMOS and PMOS transistors having different gate dielectrics. The different gate dielectrics may be formed, for example, by a subtractive process. The gate dielectrics may differ in material, thickness, or formation techniques, as a few examples.

Abstract translation: 互补金属氧化物半导体集成电路可以由具有不同栅极电介质的NMOS和PMOS晶体管形成。 可以例如通过减法处理形成不同的栅极电介质。 作为几个示例，栅极电介质可能在材料，厚度或形成技术上不同。

公开(公告)号：EP2382652A4

公开(公告)日：2013-03-20

申请号：EP09837050

申请日：2009-12-23

Applicant: INTEL CORP

Inventor： HUDAIT MANTU ,  PILLARISETTY RAVI ,  RADOSAVLJEVIC MARKO ,  DEWY GILBERT ,  RAKSHIT TITASH ,  KAVALIEROS JACK ,  TSAI WILMAN ,  MAJHI PRASHANT

IPC: H01L21/336 ,  H01L21/285 ,  H01L21/768 ,  H01L29/165 ,  H01L29/417 ,  H01L29/778 ,  H01L29/78

CPC classification number: H01L29/66431 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76805 ,  H01L29/152 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7848 ,  H01L29/802

Abstract: Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.

Abstract translation: 所描述的实施例包括具有金属源/漏极的应变晶体管量子阱（QW）沟道区，以及保形再生长源/漏极，以在MOS沟道区中赋予单轴应变。 沟道层的去除部分可以填充具有不同于沟道材料的晶格间距的连接材料，以引起沟道中的单轴应变，以及在沟道层中引起的双轴应变 顶部阻挡层和量子阱的底部缓冲层。

公开(公告)号：EP2519968A4

公开(公告)日：2015-08-05

申请号：EP10844174

申请日：2010-12-08

Applicant: INTEL CORP

Inventor： PILLARISETTY RAVI ,  KAVALIEROS JACK ,  MUKHERJEE NILOY ,  RADOSAVLJEVIC MARKO ,  CHAU ROBERT S ,  SHAH UDAY ,  DEWEY GILBERT ,  RAKSHIT TITASH ,  METZ MATHEW V

IPC: H01L21/8238 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/336 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778 ,  H01L29/78

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/7786 ,  H01L29/785

公开(公告)号：EP3127162A4

公开(公告)日：2017-11-22

申请号：EP14886770

申请日：2014-03-27

Applicant: INTEL CORP

Inventor： PILLARISETTY RAVI ,  LE VAN ,  RACHMADY WILLY ,  KOTLYAR ROZA ,  RADOSVLJEVIC MARKO ,  THEN HAN WUI ,  DASGUPTA SANSAPTAK ,  DEWEY GILBERT ,  CHU-KUNG BENJAMIN ,  KAVALIEROS JACK

IPC: H01L29/78 ,  H01L27/11

CPC classification number: H01L29/161 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Techniques related to transistors and integrated circuits having germanium tin, systems incorporating such transistors, and methods for forming them are discussed. Such transistors include a channel region that comprises a germanium tin portion of a fin such that the fin includes a buffer layer disposed over a substrate and the germanium tin portion disposed over the buffer layer.

公开(公告)号：WO2007078957A3

公开(公告)日：2007-08-30

申请号：PCT/US2006048554

申请日：2006-12-18

Applicant: INTEL CORP ,  DOYLE BRIAN S ,  BRASK JUSTIN K ,  MAJUMDAR AMLAN ,  DATTA SUMAN ,  KAVALIEROS JACK ,  RADOSAVLJEVIC MARKO ,  CHAU ROBERT S

Inventor： DOYLE BRIAN S ,  BRASK JUSTIN K ,  MAJUMDAR AMLAN ,  DATTA SUMAN ,  KAVALIEROS JACK ,  RADOSAVLJEVIC MARKO ,  CHAU ROBERT S

IPC: H01L21/336 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7848

Abstract: The fabrication of a tri-gate transistor formed with a replacement gate process is described. A nitride dummy gate, in one embodiment, is used allowing the growth of epitaxial source and drain regions immediately adjacent to the dummy gate. This reduces the external resistance.

Abstract translation: 描述了用替代栅极工艺形成的三栅极晶体管的制造。 在一个实施例中，使用氮化物伪栅极，允许直接与伪栅极相邻的外延源极和漏极区的生长。 这减少了外部电阻。