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公开(公告)号：DE112006002154T5
公开(公告)日：2008-06-26
申请号：DE112006002154
申请日：2006-08-03
Applicant: INTEL CORP
Inventor： MANDELBLAT JULIUS , MEHALEL MOTY , MENDELSON AVI , NAVEH ALON
IPC: G06F1/32
Abstract: Systems and methods of dynamic memory for power reduction are described with respect to a memory with a coupled sleep device. In one embodiment, the operating requirements can reflect amount of memory required to perform commensurate operations. Memory power management logic is used to coordinate memory requirements with operating requirements. The sleep device is able to enable or disable the memory based on the requirements to reduce power consumption.
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公开(公告)号：WO2006028652A3
公开(公告)日：2006-07-06
申请号：PCT/US2005028699
申请日：2005-08-12
Applicant: INTEL CORP , NAVEH ALON , MENDELSON AVI , ANATI ITTAI , WEISSMAN ELIEZER
Inventor： NAVEH ALON , MENDELSON AVI , ANATI ITTAI , WEISSMAN ELIEZER
IPC: G06F1/32
CPC classification number: G06F1/3287 , G06F1/3203 , Y02D10/171 , Y02D50/20
Abstract: Systems and methods of managing processors provide for detecting a command at a core of a processor having a plurality of cores, where the command requests a transition of the core to an idle state. Power consumption of the core is managed based on the command and an idle state status of each of the plurality of cores.
Abstract translation: 管理处理器的系统和方法提供用于检测具有多个核的处理器的核心处的命令，其中命令请求核到空闲状态。 基于多个核心中的每一个的命令和空闲状态来管理核心的功耗。
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公开(公告)号：DE10297624T5
公开(公告)日：2004-11-25
申请号：DE10297624
申请日：2002-12-27
Applicant: INTEL CORP
Inventor： ROSNER RONI , MENDELSON AVI
Abstract: In an embodiment, a method includes receiving a binary of a program code. The binary is based on a first instruction set architecture. The method also includes translating the binary, wherein the translated binary is based on a combination of the first instruction set architecture and a second instruction set architecture.
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Patent Agency Ranking
公开(公告)号：WO2010056587A3
公开(公告)日：2010-08-26
申请号：PCT/US2009063368
申请日：2009-11-05
Applicant: INTEL CORP , CHEN HU , GAO YING , XIAOCHENG ZHOU , YAN SHOUMENG , ZHANG PEINAN , RAJAGOPALAN MOHAN , FANG JESSE , MENDELSON AVI , SAHA BRATIN
Inventor： CHEN HU , GAO YING , XIAOCHENG ZHOU , YAN SHOUMENG , ZHANG PEINAN , FANG JESSE , MENDELSON AVI , SAHA BRATIN
IPC: G06F15/167 , G06F9/46 , G06F13/14
CPC classification number: G06F9/544 , G06F12/0815 , G06F12/084 , G06F12/1009 , G06F12/1063 , G06F12/1072 , G06F12/1081 , G06F12/109 , G06F2212/161 , G06F2212/622 , G06F2212/656 , G06F2212/657 , G06F2212/682 , G06T1/20 , G06T1/60
Abstract: Embodiments of the invention provide a programming model for CPU-GPU platforms. In particular, embodiments of the invention provide a uniform programming model for both integrated and discrete devices. The model also works uniformly for multiple GPU cards and hybrid GPU systems (discrete and integrated). This allows software vendors to write a single application stack and target it to all the different platforms. Additionally, embodiments of the invention provide a shared memory model between the CPU and GPU. Instead of sharing the entire virtual address space, only a part of the virtual address space needs to be shared. This allows efficient implementation in both discrete and integrated settings.
Abstract translation: 本发明的实施例提供了一种用于CPU-GPU平台的编程模型。 特别地，本发明的实施例为集成和分立设备提供统一的编程模型。 该模型还适用于多个GPU卡和混合GPU系统（分立和集成）。 这允许软件供应商编写单个应用程序堆栈并将其定位到所有不同的平台。 另外，本发明的实施例提供了CPU和GPU之间的共享存储器模型。 而不是共享整个虚拟地址空间，只需要共享虚拟地址空间的一部分。 这允许在离散和集成设置中有效实现。
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公开(公告)号：WO2007024435A3
公开(公告)日：2007-11-29
申请号：PCT/US2006030201
申请日：2006-08-03
Applicant: INTEL CORP , MANDELBLAT JULIUS , MEHALEL MOTY , MENDELSON AVI , NAVEH ALON
Inventor： MANDELBLAT JULIUS , MEHALEL MOTY , MENDELSON AVI , NAVEH ALON
CPC classification number: G06F1/3275 , G06F1/3225 , G06F12/0864 , G06F2212/1028 , G06F2212/601 , Y02D10/13 , Y02D10/14 , Y02D50/20
Abstract: Systems and methods of dynamic memory for power reduction are described with respect to a memory with a coupled sleep device. In one embodiment, the operating requirements can reflect amount of memory required to perform commensurate operations. Memory power management logic is used to coordinate memory requirements with operating requirements. The sleep device is able to enable or disable the memory based on the requirements to reduce power consumption.
Abstract translation: 关于具有耦合的睡眠设备的存储器描述用于功率降低的动态存储器的系统和方法。 在一个实施例中，操作要求可以反映执行相应操作所需的内存量。 内存电源管理逻辑用于根据操作要求来协调内存需求。 睡眠设备能够基于要求来启用或禁用内存，以降低功耗。
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公开(公告)号：WO2006071945A2
公开(公告)日：2006-07-06
申请号：PCT/US2005047277
申请日：2005-12-28
Applicant: INTEL CORP , ROTEM EFRAIM , BERKOVITZ ARIEL , MENDELSON AVI , NAVEH ALON
Inventor： ROTEM EFRAIM , BERKOVITZ ARIEL , MENDELSON AVI , NAVEH ALON
CPC classification number: G06F1/3203 , G06F1/3296 , Y02D10/172
Abstract: System, apparatus, method and article to manage power for a mobile device are described. The apparatus may include a power management module to save an operating context for a processor to at least one memory unit, and reduce power to the processor below a context retention point. Other embodiments are described and claimed.
Abstract translation: 描述了用于管理移动设备的功率的系统，设备，方法和文章。 该装置可以包括电源管理模块，用于将处理器的操作上下文保存到至少一个存储器单元，并且在上下文保持点下方降低处理器的功率。 描述和要求保护其他实施例。
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公开(公告)号：WO2006028652A8
公开(公告)日：2006-04-27
申请号：PCT/US2005028699
申请日：2005-08-12
Applicant: INTEL CORP , NAVEH ALON , MENDELSON AVI , ANATI ITTAI , WEISSMANN ELIEZER
Inventor： NAVEH ALON , MENDELSON AVI , ANATI ITTAI , WEISSMANN ELIEZER
IPC: G06F1/32
CPC classification number: G06F1/3287 , G06F1/3203 , Y02D10/171 , Y02D50/20
Abstract: Systems and methods of managing processors provide for detecting a command at a core of a processor having a plurality of cores, where the command requests a transition of the core to an idle state. Power consumption of the core is managed based on the command and an idle state status of each of the plurality of cores.
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公开(公告)号：EP2386087A4
公开(公告)日：2013-02-27
申请号：EP09826579
申请日：2009-11-05
Applicant: INTEL CORP , RAJAGOPALAN MOHAN
Inventor： CHEN HU , GAO YING , XIAOCHENG ZHOU , YAN SHOUMENG , ZHANG PEINAN , FANG JESSE , MENDELSON AVI , SAHA BRATIN
IPC: G06F15/167 , G06F9/46 , G06F9/54 , G06F12/10 , G06F13/14
CPC classification number: G06F9/544 , G06F12/0815 , G06F12/084 , G06F12/1009 , G06F12/1063 , G06F12/1072 , G06F12/1081 , G06F12/109 , G06F2212/161 , G06F2212/622 , G06F2212/656 , G06F2212/657 , G06F2212/682 , G06T1/20 , G06T1/60
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