EMBEDDED TRANSPORT ACCELERATION ARCHITECTURE
    1.
    发明申请
    EMBEDDED TRANSPORT ACCELERATION ARCHITECTURE 审中-公开
    嵌入式运输加速建筑

    公开(公告)号:WO2004051489A3

    公开(公告)日:2004-11-04

    申请号:PCT/US0337254

    申请日:2003-11-20

    Applicant: INTEL CORP

    Abstract: An apparatus and a system may include an adaptation module, a plurality of Direct Transport Interfaces DTIs (108), a DTI accelerator (120), and a Transport Control Protocol/Internet Protocol TCP/IP accelerator (150). The adaptation module (104) may provide a translated sockets call from an application program (132) to one of the DTIs, where an included set of memory structures may couple the translated sockets call to the DTI accelerator, which may in turn couple the set of memory structures to the TCP/IP accelerator. An article may include data causing a machine to perform a method including: receiving an application program sockets call at the adaptation module, deriving a translated sockets call from the application program sockets call, receiving the translated sockets call at a DTI, coupling the translated sockets call to a DTI accelerator using a set of memory structures in the DTI, and coupling the set of memory structures to a TCP/IP accelerator.

    Abstract translation: 装置和系统可以包括适配模块,多个直接传输接口DTI(108),DTI加速器(120)和传输控制协议/因特网协议TCP / IP加速器(150)。 适配模块(104)可以将应用程序(132)的翻译套接字调用提供给DTI中的一个,其中所包含的一组存储器结构可以将翻译的套接字调用耦合到DTI加速器,DTI加速器可以依次耦合该组 的内存结构到TCP / IP加速器。 文章可以包括导致​​机器执行方法的数据,包括:在适配模块处接收应用程序套接字呼叫,从应用程序套接字呼叫导出翻译的套接字呼叫,在DTI处接收翻译的套接字调用,将转换的套接字 使用DTI中的一组存储器结构调用DTI加速器,并将该组内存结构耦合到TCP / IP加速器。

    2.
    发明专利
    未知

    公开(公告)号:AT426987T

    公开(公告)日:2009-04-15

    申请号:AT04756431

    申请日:2004-06-29

    Applicant: INTEL CORP

    Abstract: In one embodiment, a method is provided. The method of this embodiment provides storing a packet header at a set of at least one page of memory allocated to storing packet headers, and storing the packet header and a packet payload at a location not in the set of at least one page of memory allocated to storing packet headers.

    3.
    发明专利
    未知

    公开(公告)号:DE602005005219T2

    公开(公告)日:2009-03-12

    申请号:DE602005005219

    申请日:2005-11-10

    Applicant: INTEL CORP

    Abstract: In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.

    4.
    发明专利
    未知

    公开(公告)号:DE602005005219D1

    公开(公告)日:2008-04-17

    申请号:DE602005005219

    申请日:2005-11-10

    Applicant: INTEL CORP

    Abstract: In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.

    5.
    发明专利
    未知

    公开(公告)号:AT388574T

    公开(公告)日:2008-03-15

    申请号:AT05826330

    申请日:2005-11-10

    Applicant: INTEL CORP

    Abstract: In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.

    Embedded transport acceleration architecture

    公开(公告)号:AU2003297302A8

    公开(公告)日:2004-06-23

    申请号:AU2003297302

    申请日:2003-11-20

    Applicant: INTEL CORP

    Abstract: An apparatus and a system may include an adaptation module, a plurality of Direct Transport Interfaces (DTIs), a DTI accelerator, and a Transport Control Protocol/Internet Protocol (TCP/IP) accelerator. The adaptation module may provide a translated sockets call from an application program to one of the DTIs, where an included set of memory structures may couple the translated sockets call to the DTI accelerator, which may in turn couple the set of memory structures to the TCP/IP accelerator. An article may include data causing a machine to perform a method including: receiving an application program sockets call at the adaptation module, deriving a translated sockets call from the application program sockets call, receiving the translated sockets call at a DTI, coupling the translated sockets call to a DTI accelerator using a set of memory structures in the DTI, and coupling the set of memory structures to a TCP/IP accelerator.

    7.
    发明专利
    未知

    公开(公告)号:DE602004020273D1

    公开(公告)日:2009-05-07

    申请号:DE602004020273

    申请日:2004-06-29

    Applicant: INTEL CORP

    Abstract: In one embodiment, a method is provided. The method of this embodiment provides storing a packet header at a set of at least one page of memory allocated to storing packet headers, and storing the packet header and a packet payload at a location not in the set of at least one page of memory allocated to storing packet headers.

    EMBEDDED TRANSPORT ACCELERATION ARCHITECTURE

    公开(公告)号:AU2003297302A1

    公开(公告)日:2004-06-23

    申请号:AU2003297302

    申请日:2003-11-20

    Applicant: INTEL CORP

    Abstract: An apparatus and a system may include an adaptation module, a plurality of Direct Transport Interfaces (DTIs), a DTI accelerator, and a Transport Control Protocol/Internet Protocol (TCP/IP) accelerator. The adaptation module may provide a translated sockets call from an application program to one of the DTIs, where an included set of memory structures may couple the translated sockets call to the DTI accelerator, which may in turn couple the set of memory structures to the TCP/IP accelerator. An article may include data causing a machine to perform a method including: receiving an application program sockets call at the adaptation module, deriving a translated sockets call from the application program sockets call, receiving the translated sockets call at a DTI, coupling the translated sockets call to a DTI accelerator using a set of memory structures in the DTI, and coupling the set of memory structures to a TCP/IP accelerator.

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