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    Control of on-die system fabric blocks
    1.
    发明专利
    Control of on-die system fabric blocks 有权
    控制面板系统织物块

    公开(公告)号：JP2014112387A

    公开(公告)日：2014-06-19

    申请号：JP2013268430

    申请日：2013-12-26

    Applicant: Intel Corp ,  インテル・コーポレーション

    Inventor： FANG ZHEN ,  MAHESH WAGH ,  JASMIN AJANOVIC ,  MICHAEL E ESPIG ,  IYER RAVISHANKAR

    IPC: G06F12/10

    CPC classification number: G06F12/1036 ,  G06F12/0292 ,  G06F12/0888 ,  G06F12/10 ,  G06F12/1027 ,  G06F12/109 ,  G06F2212/206

    Abstract: PROBLEM TO BE SOLVED: To provide methods and apparatus for control of On-Die System Fabric (OSF) blocks.SOLUTION: An apparatus comprises: an OSF to couple a processor to a logic block using a physical address; and a memory to store in response to a user-level request a page table including a shadow address corresponding to the physical address, a virtual address corresponding to the physical address and an alias virtual address corresponding to the shadow address. A logic circuit (e.g., present in the OSF) may determine the physical address from the shadow address.

    Abstract translation: 要解决的问题：提供用于控制片上系统结构（OSF）块的方法和装置。解决方案：一种装置，包括：使用物理地址将处理器耦合到逻辑块的OSF; 以及存储器，用于响应于用户级请求存储包括与物理地址相对应的影子地址的页表，与物理地址相对应的虚拟地址和与影子地址相对应的别名虚拟地址。 逻辑电路（例如存在于OSF中）可以根据影子地址确定物理地址。

    Method for automatically using superpage for stack memory allocation
    2.
    发明专利
    Method for automatically using superpage for stack memory allocation 有权
    用于自动使用超级存储器分配的方法

    公开(公告)号：JP2011014131A

    公开(公告)日：2011-01-20

    申请号：JP2010123238

    申请日：2010-05-28

    Applicant: Intel Corp ,  インテル・コーポレーション

    Inventor： ZHAO LI ,  FANG ZHEN ,  IYER RAVISHANKAR ,  NEWELL DONALD

    IPC: G06F12/10

    CPC classification number: G06F12/1027 ,  G06F2212/652

    Abstract: PROBLEM TO BE SOLVED: To prevent TLB (conversion index buffer) errors and page faults which tend to lead to a large time loss by stack development.SOLUTION: The invention includes a page fault handler to create page table entries and TLB entries in response to a page fault, to determine if the page fault results from stack access, to create a superpage table entry if the page fault results from stack access, and to create a TLB entry for the superpage.

    Abstract translation: 要解决的问题：为了防止倾向于通过堆栈开发导致大的时间损失的TLB（转换索引缓冲器）错误和页面错误。解决方案：本发明包括一个页面错误处理程序来创建页面表项和TLB条目以响应于 页面错误，以确定页面故障是否从堆栈访问，如果页面错误从堆栈访问结果创建超级页表项，并为超级页面创建一个TLB条目。

    CIRCUITRY TO SELECT, AT LEAST IN PART, AT LEAST ONE MEMORY
    5.
    发明申请
    CIRCUITRY TO SELECT, AT LEAST IN PART, AT LEAST ONE MEMORY 审中-公开
    电路选择，至少一部分，至少一个记忆

    公开(公告)号：WO2012102989A2

    公开(公告)日：2012-08-02

    申请号：PCT/US2012022170

    申请日：2012-01-23

    Applicant: INTEL CORP ,  FANG ZHEN ,  ZHAO LI ,  IYER RAVISHANKAR ,  MAKINENI SRIHARI ,  LIAO GUANGDENG

    Inventor： FANG ZHEN ,  ZHAO LI ,  IYER RAVISHANKAR ,  MAKINENI SRIHARI ,  LIAO GUANGDENG

    IPC: G06F1/00 ,  G06F12/00 ,  G06F13/14

    CPC classification number: G06F12/0813 ,  Y02D10/13

    Abstract: An embodiment may include circuitry to select, at least in part, from a plurality of memories, at least one memory to store data. The memories may be associated with respective processor cores. The circuitry may select, at least in part, the at least one memory based at least in part upon whether the data is included in at least one page that spans multiple memory lines that is to be processed by at least one of the processor cores. If the data is included in the at least one page, the circuitry may select, at least in part, the at least one memory, such that the at least one memory is proximate to the at least one of the processor cores. Many alternatives, variations, and modifications are possible.

    Abstract translation: 一个实施例可以包括至少部分地从多个存储器中选择至少一个存储器来存储数据的电路。 存储器可以与相应的处理器核心相关联。 该电路至少部分地至少部分地选择至少一个存储器，该至少一个存储器至少部分地基于是否将数据包括在跨越由至少一个处理器核处理的多个存储器线的至少一个页面中。 如果数据被包括在至少一个页面中，则电路可以至少部分地选择至少一个存储器，使得至少一个存储器靠近该至少一个处理器核心。 许多替代方案，变化和修改是可能的。

    PRIORITY BASED THROTTLING FOR POWER/PERFORMANCE QUALITY OF SERVICE
    6.
    发明申请
    PRIORITY BASED THROTTLING FOR POWER/PERFORMANCE QUALITY OF SERVICE 审中-公开
    基于优先级的电力/性能质量服务质量

    公开(公告)号：WO2008124455A3

    公开(公告)日：2008-12-24

    申请号：PCT/US2008059172

    申请日：2008-04-02

    Applicant: INTEL CORP ,  ILLIKKAL RAMESH KUMAR ,  IYER RAVISHANKAR ,  MOSES JAIDEEP ,  NEWELL DON ,  FOSSUM TRYGGVE

    Inventor： ILLIKKAL RAMESH KUMAR ,  IYER RAVISHANKAR ,  MOSES JAIDEEP ,  NEWELL DON ,  FOSSUM TRYGGVE

    IPC: G06F1/26

    CPC classification number: G06F9/5077 ,  G06F9/5094 ,  G06F2209/504 ,  Y02D10/22 ,  Y02D10/36

    Abstract: A method and apparatus for throttling power and/or performance of processing elements based on a priority of software entities is herein described. Priority aware power management logic receives priority levels of software entities and modifies operating points of processing elements associated with the software entities accordingly. Therefore, in a power savings mode, processing elements executing low priority applications/tasks are reduced to a lower operating point, i.e. lower voltage, lower frequency, throttled instruction issue, throttled memory accesses, and/or less access to shared resources. In addition, utilization logic potentially trackes utilization of a resource per priority level, which allows the power manager to determine operating points based on the affect of each priority level on each other from the perspective of the resources themselves. Moreover, a software entity itself may assign operating points, which the power manager enforces.

    Abstract translation: 这里描述了一种基于软件实体的优先级来节制处理元件的功率和/或性能的方法和装置。 优先级感知功率管理逻辑接收软件实体的优先级，并相应地修改与软件实体相关联的处理元件的工作点。 因此，在省电模式中，执行低优先级应用/任务的处理元件被减少到较低的工作点，即较低的电压，较低的频率，节流的指令问题，节流的存储器访问和/或较少的对共享资源的访问。 此外，利用逻辑潜在地追踪每个优先级的资源的利用率，这允许电力管理者从资源本身的角度基于彼此的每个优先级的影响来确定工作点。 此外，软件实体本身可以分配功率管理器执行的操作点。

    УСТРОЙСТВО, СПОСОБ И СИСТЕМА УПРАВЛЕНИЯ МАТРИЦАМИ
    8.
    发明专利
    УСТРОЙСТВО, СПОСОБ И СИСТЕМА УПРАВЛЕНИЯ МАТРИЦАМИ 未知

    公开(公告)号：RU2491616C2

    公开(公告)日：2013-08-27

    申请号：RU2011141892

    申请日：2010-03-03

    Applicant: INTEL CORP

    Inventor： FANG ZHEN ,  WAGH MAHESH ,  AJANOVIC JASMIN ,  ESPIG MICHAEL E ,  IYER RAVISHANKAR

    IPC: G06F12/02

    Abstract: Изобретениеотноситсяк вычислительнойтехнике. Техническийрезультатзаключаетсяв увеличениибыстродействия. Устройствоуправленияматрицамисодержиткоммутирующуюматрицусистемынакристалле (OSF), используемуюдлясвязипроцессорас логическимблоком, ипамятьдляхранениятеневогоадреса, соответствующегофизическомуадресу, вответназапроснауровнепользователя, вкотором OSF содержитлогикудляопределенияфизическогоадресаизтеневогоадреса, выполненнуюс возможностьюопределятьфизическийадреси инвертироватьодинилинескольконаивысшихбитовтеневогоадреса, чтобыопределитьфизическийадрес. 3 н. и 24 з.п. ф-лы, 7 ил.

    9.
    发明专利
    未知

    公开(公告)号：DE102008016180A1

    公开(公告)日：2008-10-23

    申请号：DE102008016180

    申请日：2008-03-28

    Applicant: INTEL CORP

    Inventor： NEWELL DONALD K ,  MOSES JAIDEEP ,  IYER RAVISHANKAR ,  ILLIKKAL RAMESHKUMAR G ,  MAKINENI SRIHARI

    IPC: G06F9/50 ,  G06F9/46

    Abstract: Embodiments of apparatuses, methods, and systems for exposing system topology to an execution environment are disclosed. In one embodiment, an apparatus includes execution cores and resources on a single integrated circuit, and topology logic. The topology logic is to populate a data structure with information regarding a relationship between the execution cores and the resources.

    Apparatus and method for a closed-loop dynamic resource allocation control framework
    10.
    发明专利
    Apparatus and method for a closed-loop dynamic resource allocation control framework 未知

    公开(公告)号：AU2020294205A1

    公开(公告)日：2022-01-20

    申请号：AU2020294205

    申请日：2020-12-22

    Applicant: INTEL CORP

    Inventor： LI BIN ,  WANG REN ,  DOSHI KSHITIJ ARUN ,  GUIM BERNAT FRANCESC ,  WANG YIPENG ,  IYER RAVISHANKAR ,  HERDRICH ANDREW ,  TAI TSUNG-YUAN ,  ZHOU ZHU ,  SUBRAMANIAN RSIKA

    IPC: G06F9/06

    Abstract: An apparatus and method for closed loop dynamic resource allocation. For example, one embodiment of a method comprises: collecting data related to usage of a plurality of resources by a plurality of workloads over one or more time periods, the workloads including priority workloads associated with one or more guaranteed performance levels and best effort workloads not associated with guaranteed performance levels; analyzing the data to identify resource reallocations from one or more of the priority workloads to one or more of the best effort workloads in one or more subsequent time periods while still maintaining the guaranteed performance levels; reallocating the resources from the priority workloads to the best effort workloads for the subsequent time periods; monitoring execution of the priority workloads with respect to the guaranteed performance level during the subsequent time periods; and preemptively reallocating resources from the best effort workloads to the priority workloads during the subsequent time periods to ensure compliance with the guaranteed performance level and responsive to detecting that the guaranteed performance level is in danger of being breached.

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