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公开(公告)号：WO2008124455A3
公开(公告)日：2008-12-24
申请号：PCT/US2008059172
申请日：2008-04-02
Applicant: INTEL CORP , ILLIKKAL RAMESH KUMAR , IYER RAVISHANKAR , MOSES JAIDEEP , NEWELL DON , FOSSUM TRYGGVE
Inventor： ILLIKKAL RAMESH KUMAR , IYER RAVISHANKAR , MOSES JAIDEEP , NEWELL DON , FOSSUM TRYGGVE
IPC: G06F1/26
CPC classification number: G06F9/5077 , G06F9/5094 , G06F2209/504 , Y02D10/22 , Y02D10/36
Abstract: A method and apparatus for throttling power and/or performance of processing elements based on a priority of software entities is herein described. Priority aware power management logic receives priority levels of software entities and modifies operating points of processing elements associated with the software entities accordingly. Therefore, in a power savings mode, processing elements executing low priority applications/tasks are reduced to a lower operating point, i.e. lower voltage, lower frequency, throttled instruction issue, throttled memory accesses, and/or less access to shared resources. In addition, utilization logic potentially trackes utilization of a resource per priority level, which allows the power manager to determine operating points based on the affect of each priority level on each other from the perspective of the resources themselves. Moreover, a software entity itself may assign operating points, which the power manager enforces.
Abstract translation: 这里描述了一种基于软件实体的优先级来节制处理元件的功率和/或性能的方法和装置。 优先级感知功率管理逻辑接收软件实体的优先级，并相应地修改与软件实体相关联的处理元件的工作点。 因此，在省电模式中，执行低优先级应用/任务的处理元件被减少到较低的工作点，即较低的电压，较低的频率，节流的指令问题，节流的存储器访问和/或较少的对共享资源的访问。 此外，利用逻辑潜在地追踪每个优先级的资源的利用率，这允许电力管理者从资源本身的角度基于彼此的每个优先级的影响来确定工作点。 此外，软件实体本身可以分配功率管理器执行的操作点。
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公开(公告)号：IN1367CHN2014A
公开(公告)日：2015-04-24
申请号：IN1367CHN2014
申请日：2014-02-20
Applicant: INTEL CORP
Inventor： HERDRICH ANDREW J , ILLIKKAL RAMESHKUMAR G , IYER RAVISHANKAR , SRINIVASAN SADOGOPAN , MOSES JAIDEEP , MAKINENI SRIHARI
Abstract: In one embodiment the present invention includes a method for receiving an interrupt from an accelerator sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core and determining whether the small core can handle a request associated with the interrupt and performing an operation corresponding to the request in the small core if the determination is in the affirmative and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.
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公开(公告)号：BRPI0810879A2
公开(公告)日：2014-10-29
申请号：BRPI0810879
申请日：2008-04-02
Applicant: INTEL CORP
Inventor： ILLIKKAL RAMESH KUMAR , IYES RAVISHANKAR , MOSES JAIDEEP , NEWELL DON , FOSSUM TRYGGVE
IPC: G06F1/26
Abstract: A method and apparatus for throttling power and/or performance of processing elements based on a priority of software entities is herein described. Priority aware power management logic receives priority levels of software entities and modifies operating points of processing elements associated with the software entities accordingly. Therefore, in a power savings mode, processing elements executing low priority applications/tasks are reduced to a lower operating point, i.e. lower voltage, lower frequency, throttled instruction issue, throttled memory accesses, and/or less access to shared resources. In addition, utilization logic potentially trackes utilization of a resource per priority level, which allows the power manager to determine operating points based on the effect of each priority level on each other from the perspective of the resources themselves. Moreover, a software entity itself may assign operating points, which the power manager enforces.
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Patent Agency Ranking
公开(公告)号：DE102008016180A1
公开(公告)日：2008-10-23
申请号：DE102008016180
申请日：2008-03-28
Applicant: INTEL CORP
Inventor： NEWELL DONALD K , MOSES JAIDEEP , IYER RAVISHANKAR , ILLIKKAL RAMESHKUMAR G , MAKINENI SRIHARI
Abstract: Embodiments of apparatuses, methods, and systems for exposing system topology to an execution environment are disclosed. In one embodiment, an apparatus includes execution cores and resources on a single integrated circuit, and topology logic. The topology logic is to populate a data structure with information regarding a relationship between the execution cores and the resources.
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公开(公告)号：DE112011105590T5
公开(公告)日：2014-07-03
申请号：DE112011105590
申请日：2011-09-06
Applicant: INTEL CORP
Inventor： HERDRICH ANDREW J , ILLIKKAL RAMESHKUMAR G , IYER RAVISHANKAR , SRINIVASAN SADAGOPAN , MOSES JAIDEEP , MAKINENI SRIHARI
Abstract: Bei einer Ausführungsform schließt die vorliegende Erfindung ein Verfahren ein, um einen Interrupt von einem Beschleuniger zu empfangen, ein Wiederaufnahmesignal direkt an einen kleinen Kern zu senden, der auf den Interrupt anspricht, und einen Teilsatz eines Ausführungsstandes des großen Kerns an den ersten kleinen Kern bereitzustellen und zu bestimmen, ob der kleine Kern eine Anforderung behandeln kann, die mit dem Interrupt verbunden ist, und eine Operation entsprechend der Anforderung im kleinen Kern auszuführen, wenn die Bestimmung bejaht wird, und andernfalls den Ausführungsstand des großen Kerns und das Wiederaufnahmesignal an den großen Kern bereitzustellen. Weitere Ausführungsformen sind beschrieben und werden beansprucht.
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公开(公告)号：GB2507696A
公开(公告)日：2014-05-07
申请号：GB201402807
申请日：2011-09-06
Applicant: INTEL CORP
Inventor： HERDRICH ANDREW J , ILLIKKAL RAMESHKUMAR G , IYER RAVISHANKAR , SRINIVASAN SADOGOPAN , MOSES JAIDEEP , MAKINENI SRIHARI
Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.
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公开(公告)号：GB2519259A
公开(公告)日：2015-04-15
申请号：GB201501454
申请日：2013-06-27
Applicant: INTEL CORP , MOSES JAIDEEP , IYER RAVISHANKAR , ILLIKKAL RAMESH , SRINIVASAN SADOGOPAN
Inventor： MOSES JAIDEEP , IYER RAVISHANKAR , ILLIKKAL RAMESH , SRINIVASAN SADOGOPAN
Abstract: A processor is described having cache circuitry and logic circuitry. The logic circuitry is to manage the entry and removal of cache lines from the cache circuitry. The logic circuitry includes storage circuitry and control circuitry. The storage circuitry is to store information identifying a set of cache lines within the cache that are in a modified state. The control circuitry is coupled to the storage circuitry to receive the information from the storage circuitry, responsive to a signal to flush the cache, and determine addresses of the cache therefrom so that the set of cache lines are read from the cache so as to avoid reading cache lines from the cache that are in an invalid or a clean state.
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公开(公告)号：DE102008016181A1
公开(公告)日：2008-12-18
申请号：DE102008016181
申请日：2008-03-28
Applicant: INTEL CORP
Inventor： ILLIKKAL RAMESH KUMAR G , IYER RAVISHANKAR , MOSES JAIDEEP , NEWELL DONALD K , FOSSUM TRYGGVE
Abstract: A method and apparatus for throttling power and/or performance of processing elements based on a priority of software entities is herein described. Priority aware power management logic receives priority levels of software entities and modifies operating points of processing elements associated with the software entities accordingly. Therefore, in a power savings mode, processing elements executing low priority applications/tasks are reduced to a lower operating point, i.e. lower voltage, lower frequency, throttled instruction issue, throttled memory accesses, and/or less access to shared resources. In addition, utilization logic potentially trackes utilization of a resource per priority level, which allows the power manager to determine operating points based on the effect of each priority level on each other from the perspective of the resources themselves. Moreover, a software entity itself may assign operating points, which the power manager enforces.
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