公开(公告)号：DE60207879T2

公开(公告)日：2006-08-17

申请号：DE60207879

申请日：2002-09-27

Applicant: INTEL CORP

Inventor： WONG LAWRENCE ,  MORROW PATRICK ,  LEU JIHPERNG ,  OTT ANDREW ,  KLOSTER GRANT

IPC: H01L21/768 ,  H01L23/532

Abstract: A dual-damascene process where first alternate ILDs are made of a first material and second alternate ILDs are made of a second material. Each material is etchable at a faster rate than the other in the presence of different etchant such as for an organic polymer and an inorganic low k material. This allows the ILDs to be deposited alternately on one another without an etchant stop layer thereby reducing capacitance.

公开(公告)号：DE112005001961T5

公开(公告)日：2007-08-09

申请号：DE112005001961

申请日：2005-07-29

Applicant: INTEL CORP

Inventor： KING SEAN ,  OTT ANDREW

IPC: H01L21/768 ,  H01L21/4763 ,  H01L23/532

Abstract: Embodiments of the invention provide a device with a hard mask layer between first and second ILD layers. The hard mask layer may have a k value approximately equal to the first and/or second ILD layers.

公开(公告)号：WO03028092A3

公开(公告)日：2003-08-28

申请号：PCT/US0231159

申请日：2002-09-27

Applicant: INTEL CORP

Inventor： WONG LAWRENCE ,  MORROW PATRICK ,  LEU JIHPERNG ,  OTT ANDREW ,  KLOSTER GRANT

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76807 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A dual damascene process where first alternate ILDs (19, 21, 30, 32) are made of a first material and second alternate ILDs (20, 31, 33) are made of a second material. Each material is etchable at a faster rate than the other in the presence of different etchant such as for an organic polymer and an inorganic low K material. This allows the ILDs to be deposited alternately on one another without an etchant stop layer thereby reducing capacitance.

Abstract translation: 一种双镶嵌工艺，其中第一替代ILD（19,21,30,32）由第一材料制成，而第二替代ILD（20,31,33）由第二材料制成。 在不同的蚀刻剂（例如有机聚合物和无机低K材料）的存在下，每种材料可以以比另一种更快的速度进行刻蚀。 这允许ILD彼此交替沉积而没有蚀刻剂停止层，从而降低电容。

公开(公告)号：GB2430803A

公开(公告)日：2007-04-04

申请号：GB0700156

申请日：2005-07-29

Applicant: INTEL CORP

Inventor： KING SEAN ,  OTT ANDREW

IPC: H01L21/768 ,  H01L21/4763 ,  H01L23/532

Abstract: Embodiments of the invention provide a device with a hard mask layer between first and second ILD layers. The hard mask layer may have a k value approximately equal to the first and/or second ILD layers.

公开(公告)号：AT312411T

公开(公告)日：2005-12-15

申请号：AT02768930

申请日：2002-09-27

Applicant: INTEL CORP

Inventor： WONG LAWRENCE ,  MORROW PATRICK ,  LEU JIHPERNG ,  OTT ANDREW ,  KLOSTER GRANT

IPC: H01L21/768 ,  H01L23/532

Abstract: A dual-damascene process where first alternate ILDs are made of a first material and second alternate ILDs are made of a second material. Each material is etchable at a faster rate than the other in the presence of different etchant such as for an organic polymer and an inorganic low k material. This allows the ILDs to be deposited alternately on one another without an etchant stop layer thereby reducing capacitance.

公开(公告)号：AU2003207483A1

公开(公告)日：2003-09-02

申请号：AU2003207483

申请日：2003-01-07

Applicant: INTEL CORP

Inventor： OTT ANDREW ,  HUA-RIEGE CHRISTINE ,  CHAMBERS STEPHEN ,  DUBIN VALERY

IPC: H01L21/288 ,  H01L21/768

Abstract: A method, apparatus, system, and machine-readable medium for an interconnect structure in a semiconductor device and its method of formation is disclosed. Embodiments comprise a carbon-doped and silicon-doped interconnect having a concentration of silicon to avoid to forming a copper silicide layer between an interconnect and a passivation layer. Some embodiments provide unexpected results in electromigration reliability in regards to activation energy and/or mean time to failure.

公开(公告)号：GB2430803B

公开(公告)日：2009-11-25

申请号：GB0700156

申请日：2005-07-29

Applicant: INTEL CORP

Inventor： KING SEAN ,  OTT ANDREW

IPC: H01L21/768 ,  H01L21/4763 ,  H01L23/532

Abstract: Embodiments of the invention provide a device with a hard mask layer between first and second ILD layers. The hard mask layer may have a k value approximately equal to the first and/or second ILD layers.

公开(公告)号：DE60207879D1

公开(公告)日：2006-01-12

申请号：DE60207879

申请日：2002-09-27

Applicant: INTEL CORP

Inventor： WONG LAWRENCE ,  MORROW PATRICK ,  LEU JIHPERNG ,  OTT ANDREW ,  KLOSTER GRANT

IPC: H01L21/768 ,  H01L23/532

Abstract: A dual-damascene process where first alternate ILDs are made of a first material and second alternate ILDs are made of a second material. Each material is etchable at a faster rate than the other in the presence of different etchant such as for an organic polymer and an inorganic low k material. This allows the ILDs to be deposited alternately on one another without an etchant stop layer thereby reducing capacitance.