公开(公告)号：DE60207879T2

公开(公告)日：2006-08-17

申请号：DE60207879

申请日：2002-09-27

Applicant: INTEL CORP

Inventor： WONG LAWRENCE ,  MORROW PATRICK ,  LEU JIHPERNG ,  OTT ANDREW ,  KLOSTER GRANT

IPC: H01L21/768 ,  H01L23/532

Abstract: A dual-damascene process where first alternate ILDs are made of a first material and second alternate ILDs are made of a second material. Each material is etchable at a faster rate than the other in the presence of different etchant such as for an organic polymer and an inorganic low k material. This allows the ILDs to be deposited alternately on one another without an etchant stop layer thereby reducing capacitance.

公开(公告)号：WO2006058009A3

公开(公告)日：2007-02-22

申请号：PCT/US2005042333

申请日：2005-11-17

Applicant: INTEL CORP ,  BOYANOV BOYAN ,  KLOSTER GRANT ,  GOODNER MICHAEL

Inventor： BOYANOV BOYAN ,  KLOSTER GRANT ,  GOODNER MICHAEL

IPC: H01L21/316 ,  H01L23/532

CPC classification number: H01L21/76835 ,  H01L21/02145 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/02318 ,  H01L21/02362 ,  H01L21/31695 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76826 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for impregnating the pores of a zeolite low-k dielectric layer with a polymer, and forming an interconnect structure therein, thus mechanically strengthening the dielectric layer and preventing metal deposits within the pores.

Abstract translation: 用聚合物浸渍沸石低k电介质层的孔，并在其中形成互连结构的方法，从而机械地增强电介质层并防止孔内的金属沉积。

公开(公告)号：AT312411T

公开(公告)日：2005-12-15

申请号：AT02768930

申请日：2002-09-27

Applicant: INTEL CORP

Inventor： WONG LAWRENCE ,  MORROW PATRICK ,  LEU JIHPERNG ,  OTT ANDREW ,  KLOSTER GRANT

IPC: H01L21/768 ,  H01L23/532

Abstract: A dual-damascene process where first alternate ILDs are made of a first material and second alternate ILDs are made of a second material. Each material is etchable at a faster rate than the other in the presence of different etchant such as for an organic polymer and an inorganic low k material. This allows the ILDs to be deposited alternately on one another without an etchant stop layer thereby reducing capacitance.

公开(公告)号：DE60207879D1

公开(公告)日：2006-01-12

申请号：DE60207879

申请日：2002-09-27

Applicant: INTEL CORP

Inventor： WONG LAWRENCE ,  MORROW PATRICK ,  LEU JIHPERNG ,  OTT ANDREW ,  KLOSTER GRANT

IPC: H01L21/768 ,  H01L23/532

Abstract: A dual-damascene process where first alternate ILDs are made of a first material and second alternate ILDs are made of a second material. Each material is etchable at a faster rate than the other in the presence of different etchant such as for an organic polymer and an inorganic low k material. This allows the ILDs to be deposited alternately on one another without an etchant stop layer thereby reducing capacitance.

公开(公告)号：WO2009158236A3

公开(公告)日：2010-04-22

申请号：PCT/US2009047467

申请日：2009-06-16

Applicant: INTEL CORP ,  RAMACHANDRARAO VIJAYAKUMAR S ,  KLOSTER GRANT ,  BOYANOV BOYAN

Inventor： RAMACHANDRARAO VIJAYAKUMAR S ,  KLOSTER GRANT ,  BOYANOV BOYAN

IPC: H01L21/31 ,  H01L21/205

CPC classification number: H01L21/3105 ,  Y10T428/249953 ,  Y10T428/249978

Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include removing a portion of at least one of Si-C bonds and CHx bonds in a dielectric material comprising a porogen material by reaction with a wet chemical, wherein the portion of Si-C and CHx bonds are converted to Si-H bonds. The Si-H bonds may be further hydrolyzed to form SiOH linkages. The SiOH linkages may then be removed by a radiation based cure, wherein a portion of the porogen material is also removed.

Abstract translation: 描述形成微电子结构的方法。 这些方法的实施方案包括通过与湿化学品反应除去包含致孔剂材料的电介质材料中的至少一个Si-C键和CHx键的一部分，其中Si-C和CHx键的部分转化为Si- H债券。 可以进一步水解Si-H键以形成SiOH键。 然后可以通过基于辐射的固化来除去SiOH键，其中一部分致孔剂材料也被除去。

公开(公告)号：WO03028092A3

公开(公告)日：2003-08-28

申请号：PCT/US0231159

申请日：2002-09-27

Applicant: INTEL CORP

Inventor： WONG LAWRENCE ,  MORROW PATRICK ,  LEU JIHPERNG ,  OTT ANDREW ,  KLOSTER GRANT

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76807 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A dual damascene process where first alternate ILDs (19, 21, 30, 32) are made of a first material and second alternate ILDs (20, 31, 33) are made of a second material. Each material is etchable at a faster rate than the other in the presence of different etchant such as for an organic polymer and an inorganic low K material. This allows the ILDs to be deposited alternately on one another without an etchant stop layer thereby reducing capacitance.

Abstract translation: 一种双镶嵌工艺，其中第一替代ILD（19,21,30,32）由第一材料制成，而第二替代ILD（20,31,33）由第二材料制成。 在不同的蚀刻剂（例如有机聚合物和无机低K材料）的存在下，每种材料可以以比另一种更快的速度进行刻蚀。 这允许ILD彼此交替沉积而没有蚀刻剂停止层，从而降低电容。

公开(公告)号：EP3235009A4

公开(公告)日：2018-07-25

申请号：EP14908638

申请日：2014-12-19

Applicant: INTEL CORP

Inventor： KLOSTER GRANT ,  CLENDENNING SCOTT B ,  HOURANI RAMI ,  LIAO SZUYA S ,  ROMERO PATRICIO E ,  GSTREIN FLORIAN

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/32 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/28194 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/31133 ,  H01L21/32 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42368 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/786

Abstract: Methods of selectively depositing high-K gate dielectric on a semiconductor structure are disclosed. The method includes providing a semiconductor structure disposed above a semiconductor substrate. The semiconductor structure is disposed beside an isolation sidewall. A sacrificial blocking layer is then selectively deposited on the isolation sidewall and not on the semiconductor structure. Thereafter, a high-K gate dielectric is deposited on the semiconductor structure, but not on the sacrificial blocking layer. Properties of the sacrificial blocking layer prevent deposition of oxide material on its surface. A thermal treatment is then performed to remove the sacrificial blocking layer, thereby forming a high-K gate dielectric only on the semiconductor structure.