公开(公告)号：JP2007183950A

公开(公告)日：2007-07-19

申请号：JP2006349809

申请日：2006-12-26

Applicant: Intel Corp ,  インテル コーポレイション

Inventor： SHAM M DATTA ,  GREINER ROBERT ,  BINNS FRANK ,  KESHAVAN TIRUVALLUR ,  PARTHASARATHY RAJESH ,  PARTHASARATHY MADHAVAN

IPC: G06F13/14

CPC classification number: G06F9/342 ,  G06F9/30174 ,  G06F12/0292 ,  G06F12/063 ,  G06F2212/206

Abstract: PROBLEM TO BE SOLVED: To expand efficiency and performance of a system while maintaining compatibility with legacy OS software. SOLUTION: A device, a system, a method, and a product work for detecting an input/output access action associated with a configuration memory address and a first memory address bit size. In some cases, the configuration memory address and associated configuration data are connected to a packet with a bit size (for example, 64 bit) of a second memory address larger than that (for example, 32 bits) of a first memory address. The packet is used for establishing compatibility with a legacy operating system communicating with a PCI (Peripheral Component Interconnect) interface-based peripheral device and a similar platform device integrated in the same package as a processor. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提高系统的效率和性能，同时保持与旧版OS软件的兼容性。 解决方案：用于检测与配置存储器地址和第一存储器地址位大小相关联的输入/输出访问动作的设备，系统，方法和产品工作。 在一些情况下，配置存储器地址和相关联的配置数据被连接到具有大于第一存储器地址（例如，32位）的第二存储器地址的位大小（例如，64位）的分组。 该数据包用于与与基于PCI（外围组件互连）接口的外围设备通信的传统操作系统和与处理器集成在同一封装中的类似平台设备建立兼容性。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：WO2012040723A3

公开(公告)日：2012-06-21

申请号：PCT/US2011053306

申请日：2011-09-26

Applicant: INTEL CORP ,  HINTON GLENN ,  RAMANUJAN RAJ ,  CAPE SCOTT J ,  PARTHASARATHY MADHAVAN ,  ZIMMERMAN DAVID ,  DOWNER WAYNE A ,  PARTHASARATHY RAJESH ,  SMITH LARRY O ,  CHAPPELL ROBERT S ,  SWAMINATHAN MUTHUKUMAR ,  MOGA ADRIAN C

Inventor： HINTON GLENN ,  RAMANUJAN RAJ ,  CAPE SCOTT J ,  PARTHASARATHY MADHAVAN ,  ZIMMERMAN DAVID ,  DOWNER WAYNE A ,  PARTHASARATHY RAJESH ,  SMITH LARRY O ,  CHAPPELL ROBERT S ,  SWAMINATHAN MUTHUKUMAR ,  MOGA ADRIAN C

IPC: G06F12/00 ,  G06F9/06 ,  G06F13/14

CPC classification number: G06F12/1027 ,  G06F12/023 ,  G06F12/0292 ,  G06F12/06 ,  G06F12/1009 ,  G06F2212/1028 ,  G06F2212/1041 ,  G06F2212/151 ,  G06F2212/205 ,  G06F2212/651 ,  Y02D10/13

Abstract: An apparatus, method, machine-readable medium, and system are disclosed. In one embodiment the apparatus is a micro-page table engine that includes logic that is capable of receiving a memory page request for a page in global memory address space. The apparatus also includes a translation lookaside buffer (TLB) that is capable of storing one or more memory page address translations. Additionally, the apparatus also has a page miss handler capable of performing a micro physical address lookup in a page miss handler tag table in response to the TLB not storing the memory page address translation for the page of memory referenced by the memory page request. The apparatus also includes memory management logic that is capable of managing the page miss handler tag table entries. The micro-page table engine allows the TLB to be an agent that determines whether data in a two-level memory hierarchy is in a hot region of memory or in a cold region of memory. When data is in the cold region of memory, the micro-page table engine fetches the data to the hot memory and a hot memory block is then pushed out to the cold memory area.

Abstract translation: 公开了一种装置，方法，机器可读介质和系统。 在一个实施例中，该装置是微页表引擎，其包括能够接收全局存储器地址空间中的页面的存储器页面请求的逻辑。 该装置还包括能够存储一个或多个存储器页面地址转换的翻译后备缓冲器（TLB）。 此外，该设备还具有能够响应于TLB不存储由存储器寻呼请求引用的存储器页面的存储器页面地址转换而在页面未命中处理器标签表中执行微物理地址查找的页面未命中处理程序。 该装置还包括能够管理页面未命中处理程序标签表条目的存储器管理逻辑。 微页表引擎允许TLB作为一个代理，确定二级存储器层次结构中的数据是在存储器的热区域还是在存储器的冷区域。 当数据处于存储器的冷区域时，微页表引擎将数据读取到热存储器，然后将热存储器块推出到冷存储器区域。

公开(公告)号：EP2619675A4

公开(公告)日：2014-06-25

申请号：EP11827736

申请日：2011-09-26

Applicant: INTEL CORP

Inventor： HINTON GLENN ,  RAMANUJAN RAJ ,  CAPE SCOTT J ,  PARTHASARATHY MADHAVAN ,  ZIMMERMAN DAVID ,  DOWNER WAYNE A ,  PARTHASARATHY RAJESH ,  SMITH LARRY O ,  CHAPPELL ROBERT S ,  SWAMINATHAN MUTHUKUMAR ,  MOGA ADRIAN C

IPC: G06F12/00 ,  G06F9/06 ,  G06F12/02 ,  G06F12/06 ,  G06F12/10 ,  G06F13/14

CPC classification number: G06F12/1027 ,  G06F12/023 ,  G06F12/0292 ,  G06F12/06 ,  G06F12/1009 ,  G06F2212/1028 ,  G06F2212/1041 ,  G06F2212/151 ,  G06F2212/205 ,  G06F2212/651 ,  Y02D10/13

Abstract: In one embodiment the apparatus is a micro-page table engine that includes logic that is capable of receiving a memory page request for a page in global memory address space. The apparatus also includes a translation lookaside buffer (TLB) that is capable of storing one or more memory page address translations. Additionally, the apparatus also has a page miss handler capable of performing a micro physical address lookup in a page miss handler tag table in response to the TLB not storing the memory page address translation for the page of memory referenced by the memory page request. The apparatus also includes memory management logic that is capable of managing the page miss handler tag table entries.