公开(公告)号：JP2008077663A

公开(公告)日：2008-04-03

申请号：JP2007244076

申请日：2007-09-20

Applicant: Intel Corp ,  インテル・コーポレーション

Inventor： ZOHAR RONEN ,  SECONI MARK ,  PARTHASARATHY RAJESH ,  CHENNUPATY SRINIVAS ,  BUXTON MARK ,  DESYLVA CHUCK

IPC: G06F17/16 ,  G06F9/30

CPC classification number: G06F17/10 ,  G06F7/48 ,  G06F7/5443 ,  G06F9/3001

Abstract: PROBLEM TO BE SOLVED: To provide a method, an apparatus, and a programming means for significantly decreasing the number of instructions required for a dot-product operation. SOLUTION: In one embodiment, the apparatus comprises an execution resource for executing a first instruction decoded to one micro operation. In response to the first instruction, the execution resource calculates the dot product of at least two source operands for a specific data type including an integer and a floating point, and stores the result value in the same register or memory location as one of the source operands. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于显着减少点产品操作所需指令数量的方法，装置和编程装置。 解决方案：在一个实施例中，该装置包括用于执行解码为一个微操作的第一指令的执行资源。 响应于第一指令，执行资源计算用于包括整数和浮点的特定数据类型的至少两个源操作数的点乘积，并将结果值存储在与源中的一个相同的寄存器或存储器位置 操作数。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007183950A

公开(公告)日：2007-07-19

申请号：JP2006349809

申请日：2006-12-26

Applicant: Intel Corp ,  インテル コーポレイション

Inventor： SHAM M DATTA ,  GREINER ROBERT ,  BINNS FRANK ,  KESHAVAN TIRUVALLUR ,  PARTHASARATHY RAJESH ,  PARTHASARATHY MADHAVAN

IPC: G06F13/14

CPC classification number: G06F9/342 ,  G06F9/30174 ,  G06F12/0292 ,  G06F12/063 ,  G06F2212/206

Abstract: PROBLEM TO BE SOLVED: To expand efficiency and performance of a system while maintaining compatibility with legacy OS software. SOLUTION: A device, a system, a method, and a product work for detecting an input/output access action associated with a configuration memory address and a first memory address bit size. In some cases, the configuration memory address and associated configuration data are connected to a packet with a bit size (for example, 64 bit) of a second memory address larger than that (for example, 32 bits) of a first memory address. The packet is used for establishing compatibility with a legacy operating system communicating with a PCI (Peripheral Component Interconnect) interface-based peripheral device and a similar platform device integrated in the same package as a processor. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提高系统的效率和性能，同时保持与旧版OS软件的兼容性。 解决方案：用于检测与配置存储器地址和第一存储器地址位大小相关联的输入/输出访问动作的设备，系统，方法和产品工作。 在一些情况下，配置存储器地址和相关联的配置数据被连接到具有大于第一存储器地址（例如，32位）的第二存储器地址的位大小（例如，64位）的分组。 该数据包用于与与基于PCI（外围组件互连）接口的外围设备通信的传统操作系统和与处理器集成在同一封装中的类似平台设备建立兼容性。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：DE112008002402T5

公开(公告)日：2010-07-15

申请号：DE112008002402

申请日：2008-08-28

Applicant: INTEL CORP

Inventor： KAUSHKI SHIVNANDAN D ,  TIRUVALLUR KESHAVAN K ,  CROSSLAND JAMES B ,  MUTHRASANALLUR SRIDHAR ,  PARTHASARATHY RAJESH ,  HOOD LUKE P

IPC: G06F13/24

公开(公告)号：WO2012040723A3

公开(公告)日：2012-06-21

申请号：PCT/US2011053306

申请日：2011-09-26

Applicant: INTEL CORP ,  HINTON GLENN ,  RAMANUJAN RAJ ,  CAPE SCOTT J ,  PARTHASARATHY MADHAVAN ,  ZIMMERMAN DAVID ,  DOWNER WAYNE A ,  PARTHASARATHY RAJESH ,  SMITH LARRY O ,  CHAPPELL ROBERT S ,  SWAMINATHAN MUTHUKUMAR ,  MOGA ADRIAN C

Inventor： HINTON GLENN ,  RAMANUJAN RAJ ,  CAPE SCOTT J ,  PARTHASARATHY MADHAVAN ,  ZIMMERMAN DAVID ,  DOWNER WAYNE A ,  PARTHASARATHY RAJESH ,  SMITH LARRY O ,  CHAPPELL ROBERT S ,  SWAMINATHAN MUTHUKUMAR ,  MOGA ADRIAN C

IPC: G06F12/00 ,  G06F9/06 ,  G06F13/14

CPC classification number: G06F12/1027 ,  G06F12/023 ,  G06F12/0292 ,  G06F12/06 ,  G06F12/1009 ,  G06F2212/1028 ,  G06F2212/1041 ,  G06F2212/151 ,  G06F2212/205 ,  G06F2212/651 ,  Y02D10/13

Abstract: An apparatus, method, machine-readable medium, and system are disclosed. In one embodiment the apparatus is a micro-page table engine that includes logic that is capable of receiving a memory page request for a page in global memory address space. The apparatus also includes a translation lookaside buffer (TLB) that is capable of storing one or more memory page address translations. Additionally, the apparatus also has a page miss handler capable of performing a micro physical address lookup in a page miss handler tag table in response to the TLB not storing the memory page address translation for the page of memory referenced by the memory page request. The apparatus also includes memory management logic that is capable of managing the page miss handler tag table entries. The micro-page table engine allows the TLB to be an agent that determines whether data in a two-level memory hierarchy is in a hot region of memory or in a cold region of memory. When data is in the cold region of memory, the micro-page table engine fetches the data to the hot memory and a hot memory block is then pushed out to the cold memory area.

Abstract translation: 公开了一种装置，方法，机器可读介质和系统。 在一个实施例中，该装置是微页表引擎，其包括能够接收全局存储器地址空间中的页面的存储器页面请求的逻辑。 该装置还包括能够存储一个或多个存储器页面地址转换的翻译后备缓冲器（TLB）。 此外，该设备还具有能够响应于TLB不存储由存储器寻呼请求引用的存储器页面的存储器页面地址转换而在页面未命中处理器标签表中执行微物理地址查找的页面未命中处理程序。 该装置还包括能够管理页面未命中处理程序标签表条目的存储器管理逻辑。 微页表引擎允许TLB作为一个代理，确定二级存储器层次结构中的数据是在存储器的热区域还是在存储器的冷区域。 当数据处于存储器的冷区域时，微页表引擎将数据读取到热存储器，然后将热存储器块推出到冷存储器区域。

公开(公告)号：DE112007002101T5

公开(公告)日：2009-07-09

申请号：DE112007002101

申请日：2007-09-20

Applicant: INTEL CORP

Inventor： ZOHAR RONEN ,  SECONI MARK ,  PARTHASARATHY RAJESH ,  CHENNUPATY SRINIVAS ,  BUXTON MARK ,  DESYLVA CHUCK ,  ABDALLAH MOHAMMAD A

IPC: G06F9/30 ,  G06F7/00 ,  G06F9/06

Abstract: Method, apparatus, and program means for performing a dot-product operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store to a storage location a result value equal to a dot-product of at least two operands.

公开(公告)号：WO2006007361A3

公开(公告)日：2007-06-07

申请号：PCT/US2005020464

申请日：2005-06-09

Applicant: INTEL CORP ,  NEIGER GILBERT ,  ANDERSON ANDREW V ,  BENNETT STEVEN M ,  BRANDT JASON ,  COTA-ROBLES ERIK ,  JAYASINGH STALINSELVARAJ ,  KAEGI ALAIN ,  MONDAL SANJOY K ,  PARTHASARATHY RAJESH ,  RODGERS DION ,  SMITH LAWRENCE O ,  UHLIG RICHARD A

Inventor： NEIGER GILBERT ,  ANDERSON ANDREW V ,  BENNETT STEVEN M ,  BRANDT JASON ,  COTA-ROBLES ERIK ,  JAYASINGH STALINSELVARAJ ,  KAEGI ALAIN ,  MONDAL SANJOY K ,  PARTHASARATHY RAJESH ,  RODGERS DION ,  SMITH LAWRENCE O ,  UHLIG RICHARD A

IPC: G06F9/445

CPC classification number: G06F9/45533 ,  G06F11/0712 ,  G06F11/0775 ,  G06F11/0787 ,  G06F11/0793

Abstract: In one embodiment, information pertaining to a first fault occurring during operation of a virtual machine (VM) is stored in a first field. A second fault is detected while delivering the first fault to the VM, and a determination is made as to whether the second fault is associated with a transition of control to a virtual machine monitor (VMM). If this determination is positive, information pertaining to the second fault is stored in a second field, and control is transitioned to the VMM.

Abstract translation: 在一个实施例中，关于在虚拟机（VM）的操作期间发生的第一故障的信息被存储在第一字段中。 在向VM提供第一故障时检测到第二故障，并且确定第二故障是否与对虚拟机监视器（VMM）的控制转换相关联。 如果该确定是肯定的，则关于第二故障的信息被存储在第二字段中，并且控制被转换到VMM。

公开(公告)号：WO2010062514A3

公开(公告)日：2010-07-22

申请号：PCT/US2009061641

申请日：2009-10-22

Applicant: INTEL CORP ,  TIRUVALLUR KESHAVAN ,  PARTHASARATHY RAJESH ,  CROSSLAND JAMES B ,  KAUSHIK SHIVNANDAN ,  HOOD LUKE

Inventor： TIRUVALLUR KESHAVAN ,  PARTHASARATHY RAJESH ,  CROSSLAND JAMES B ,  KAUSHIK SHIVNANDAN ,  HOOD LUKE

IPC: G06F13/24 ,  G06F13/20 ,  G06F13/38

CPC classification number: G06F13/24

Abstract: A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APIC) is interfaced via a set of of bits within an APIC interface register using various interface instructions or operations, without using memory-mapped input/output (MMIO).

Abstract translation: 一种在计算机系统内实现高效中断通信的技术。 在一个实施例中，高级可编程中断控制器（APIC）通过使用各种接口指令或操作的APIC接口寄存器内的一组位进行接口，而不使用存储器映射的输入/输出（MMIO）。

公开(公告)号：DE102009050983A1

公开(公告)日：2010-06-02

申请号：DE102009050983

申请日：2009-10-28

Applicant: INTEL CORP

Inventor： TIRUVALLUR KESHAVAN ,  PARTHASARATHY RAJESH ,  CROSSLAND JAMES B ,  KAUSHIK SHIVNANDAN ,  HOOD LUKE

IPC: G06F13/24

Abstract: A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APlC) is interfaced via a set of bits within an APIC interface register using various interface instructions or operations, without using memory-mapped input/output (MMIO).

公开(公告)号：EP2619675A4

公开(公告)日：2014-06-25

申请号：EP11827736

申请日：2011-09-26

Applicant: INTEL CORP

Inventor： HINTON GLENN ,  RAMANUJAN RAJ ,  CAPE SCOTT J ,  PARTHASARATHY MADHAVAN ,  ZIMMERMAN DAVID ,  DOWNER WAYNE A ,  PARTHASARATHY RAJESH ,  SMITH LARRY O ,  CHAPPELL ROBERT S ,  SWAMINATHAN MUTHUKUMAR ,  MOGA ADRIAN C

IPC: G06F12/00 ,  G06F9/06 ,  G06F12/02 ,  G06F12/06 ,  G06F12/10 ,  G06F13/14

CPC classification number: G06F12/1027 ,  G06F12/023 ,  G06F12/0292 ,  G06F12/06 ,  G06F12/1009 ,  G06F2212/1028 ,  G06F2212/1041 ,  G06F2212/151 ,  G06F2212/205 ,  G06F2212/651 ,  Y02D10/13

Abstract: In one embodiment the apparatus is a micro-page table engine that includes logic that is capable of receiving a memory page request for a page in global memory address space. The apparatus also includes a translation lookaside buffer (TLB) that is capable of storing one or more memory page address translations. Additionally, the apparatus also has a page miss handler capable of performing a micro physical address lookup in a page miss handler tag table in response to the TLB not storing the memory page address translation for the page of memory referenced by the memory page request. The apparatus also includes memory management logic that is capable of managing the page miss handler tag table entries.