公开(公告)号：KR20180019523A

公开(公告)日：2018-02-26

申请号：KR20177033117

申请日：2015-06-18

Applicant: INTEL CORP

Inventor： ROMERO PATRICIO E

IPC: C07F1/02 ,  C23C16/18 ,  C23C16/455

CPC classification number: C07F1/005 ,  C23C16/04 ,  C23C16/18 ,  H01L21/28562 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76849 ,  H01L21/76897

Abstract: 제2 또는제3 행전이금속(예를들어, 텅스텐또는루테늄) 박막들의퇴적을위한선천적으로선택적인전구체들이설명된다. 예에서, 제2 또는제3 행전이금속착물형성을위한리간드프레임워크는리튬착물을포함한다.

Abstract translation: 描述了用于沉积第二或第三金属（例如钨或钌）薄膜的通常选择性前体。 在一个实例中，用于形成第二或第三金属络合物的配体骨架包含锂络合物。

公开(公告)号：KR20180016992A

公开(公告)日：2018-02-20

申请号：KR20177033076

申请日：2015-06-17

Applicant: INTEL CORP

Inventor： ROMERO PATRICIO E ,  PLOMBON JOHN J

IPC: H01L21/3213 ,  H01L21/3065 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L43/12

CPC classification number: H01L21/32135 ,  H01L21/76834 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53209 ,  H01L43/12

Abstract: 디바이스제조를위한산화물층들의원자층 제거에의한전이금속건식에칭, 및그 결과인디바이스들이설명된다. 예에서, 막을에칭하는방법은전이금속-함유막의전이금속종의표면층을분자산화제종과반응시키는단계를포함한다. 본방법은반응된분자산화제종의휘발성단편들을제거하여전이금속종의산화표면층을제공하는단계를또한포함한다. 본방법은전이금속종의산화표면층을분자에칭제와반응시키는단계를또한포함한다. 본방법은전이금속종의반응된산화표면층 및반응된분자에칭제를휘발화에의해제거하는단계를또한포함한다.

Abstract translation: 描述了通过原子层去除用于器件制造的氧化物层的过渡金属干法刻蚀，以及所得到的器件。 在一个实例中，蚀刻膜的方法包括使含过渡金属膜的过渡金属物质的表面层与分子氧化剂物质反应。 该方法还包括除去反应后的分子氧化剂物质的挥发性碎片以提供过渡金属物质的氧化表面层。 该方法还包括使过渡金属物质的氧化表面层与分子蚀刻剂反应的步骤。 该方法还包括通过挥发除去反应后的过渡金属物质的氧化表面层和反应后的分子蚀刻剂。

公开(公告)号：EP3235009A4

公开(公告)日：2018-07-25

申请号：EP14908638

申请日：2014-12-19

Applicant: INTEL CORP

Inventor： KLOSTER GRANT ,  CLENDENNING SCOTT B ,  HOURANI RAMI ,  LIAO SZUYA S ,  ROMERO PATRICIO E ,  GSTREIN FLORIAN

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/32 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/28194 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/31133 ,  H01L21/32 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42368 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/786

Abstract: Methods of selectively depositing high-K gate dielectric on a semiconductor structure are disclosed. The method includes providing a semiconductor structure disposed above a semiconductor substrate. The semiconductor structure is disposed beside an isolation sidewall. A sacrificial blocking layer is then selectively deposited on the isolation sidewall and not on the semiconductor structure. Thereafter, a high-K gate dielectric is deposited on the semiconductor structure, but not on the sacrificial blocking layer. Properties of the sacrificial blocking layer prevent deposition of oxide material on its surface. A thermal treatment is then performed to remove the sacrificial blocking layer, thereby forming a high-K gate dielectric only on the semiconductor structure.

公开(公告)号：EP2761663A4

公开(公告)日：2015-07-22

申请号：EP11873468

申请日：2011-09-29

Applicant: INTEL CORP

Inventor： ROMERO PATRICIO E ,  CLENDENNING SCOTT B

IPC: H01L21/285 ,  C23C16/30 ,  C23C16/42 ,  H01L21/3205 ,  H01L21/336 ,  H01L29/06 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/28556 ,  C23C16/30 ,  C23C16/42 ,  H01L21/28506 ,  H01L21/28562 ,  H01L21/28575 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53266 ,  H01L29/04 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/161 ,  H01L29/201 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/49 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66522 ,  H01L29/66568 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP3198652A4

公开(公告)日：2018-05-30

申请号：EP14902843

申请日：2014-09-26

Applicant: INTEL CORP

Inventor： CLENDENNING SCOTT B ,  LIAO SZUYA S ,  GSTREIN FLORIAN ,  HOURANI RAMI ,  ROMERO PATRICIO E ,  KLOSTER GRANT M ,  MITAN MARTIN M

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/66

CPC classification number: H01L29/0673 ,  H01L21/265 ,  H01L21/28247 ,  H01L29/42364 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.

公开(公告)号：EP3122918A4

公开(公告)日：2018-03-14

申请号：EP14887657

申请日：2014-03-27

Applicant: INTEL CORP

Inventor： BLACKWELL JAMES M ,  ROMERO PATRICIO E ,  CLENDENNING SCOTT B ,  KLOSTER GRANT M ,  GSTREIN FLORIAN ,  SIMKA HARSONO S ,  ZIMMERMAN PAUL A ,  BRISTOL ROBERT L

IPC: H01L21/285 ,  C23C16/455 ,  C23C16/52 ,  H01L21/033

CPC classification number: C23C16/45553 ,  C23C16/18 ,  C23C16/482 ,  H01L21/0337 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76816 ,  H01L21/76879 ,  H01L21/76897 ,  H01L29/66795

Abstract: Precursor and process design for photo-assisted metal atomic layer deposition (ALD) and chemical vapor deposition (CVD) is described. In an example, a method of fabricating a thin metal film involves introducing precursor molecules proximate to a surface on or above a substrate, each of the precursor molecules having one or more metal centers surrounded by ligands. The method also involves depositing a metal layer on the surface by dissociating the ligands from the precursor molecules using a photo-assisted process.

公开(公告)号：EP3155655A4

公开(公告)日：2018-03-21

申请号：EP14895432

申请日：2014-06-16

Applicant: INTEL CORP

Inventor： ROBERTS JEANETTE M ,  ROMERO PATRICIO E ,  CLENDENNING SCOTT B ,  JEZEWSKI CHRISTOPHER J ,  CHEBIAM RAMANAN V

IPC: H01L21/285 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/53238 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/288 ,  H01L21/3215 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76855 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L24/17 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/15311 ,  H05K1/181 ,  H05K2201/10734 ,  H01L2924/00

Abstract: Embodiments of the present disclosure describe a selective diffusion barrier between metals of an integrated circuit (IC) device and associated techniques and configurations. In one embodiment, an apparatus includes a dielectric material, a first interconnect structure comprising a first metal disposed in the dielectric material, a second interconnect structure comprising a second metal disposed in the dielectric material and electrically coupled with the first interconnect structure and a diffusion barrier disposed at an interface between the first interconnect structure and the second interconnect structure, wherein the first metal and the second metal have a different chemical composition, material of the diffusion barrier and the second metal have a different chemical composition and material of the diffusion barrier is not disposed directly between the second metal and the dielectric material. Other embodiments may be described and/or claimed.

公开(公告)号：EP3050084A4

公开(公告)日：2017-05-24

申请号：EP13894765

申请日：2013-09-27

Applicant: INTEL CORP

Inventor： BRISTOL ROBERT L ,  BLACKWELL JAMES M ,  CLENDENNING SCOTT B ,  GSTREIN FLORIAN ,  HAN EUNGNAK ,  KLOSTER GRANT M ,  ROBERTS JEANETTE M ,  ROMERO PATRICIO E ,  HOURANI RAMI

IPC: H01L21/768 ,  H01L21/285 ,  H01L21/288 ,  H01L21/32

CPC classification number: H01L23/528 ,  H01L21/28562 ,  H01L21/288 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/311 ,  H01L21/32 ,  H01L21/32051 ,  H01L21/321 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00