公开(公告)号：DE3500254A1

公开(公告)日：1986-07-10

申请号：DE3500254

申请日：1985-01-05

Applicant: INTEL CORP

Inventor： TETRICK RAYMOND S ,  BEASTON JOHN ,  FARRELL ROBERT L ,  SARABI ALIREZA ,  BALACHANDRAN SUDARSHAN ,  JACKS JUN EDWIN L ,  KASSELL STEVEN D

IPC: G06F13/374 ,  G06F13/42 ,  G06F13/40 ,  H04L25/02

Abstract: The bus structure comprises both a parallel bus (35) and a series bus (37), which connect to one another data processing units (25, 26) and peripheral devices (30), jointly referred to as "stations", in order to permit the interchange of data and messages at high speed using a minimum of "handshake" events before the actual data transmission. The serial and parallel bus protocols are controlled by message control devices (44, 50), which are coupled to each participating station. A local bus (56) is coupled to processing stations (25, 26) within the system in such a way that access can be made to local memories (54) and secondary processing resources (57) without adversely affecting the data traffic via the parallel bus (35). A direct access by other bus stations to resources (54) coupled to the local bus (56) of one station is likewise controlled by the message control device (44).

公开(公告)号：DE3500254C2

公开(公告)日：1997-01-09

申请号：DE3500254

申请日：1985-01-05

Applicant: INTEL CORP

Inventor： TETRICK RAYMOND S ,  BEASTON JOHN ,  FARRELL ROBERT L ,  SARABI ALIREZA ,  BALACHANDRAN SUDARSHAN ,  JACKS JUN EDWIN L ,  KASSELL STEVEN D

IPC: G06F13/374 ,  G06F13/42 ,  G06F13/40 ,  H04L25/02

公开(公告)号：DE3500248A1

公开(公告)日：1986-07-10

申请号：DE3500248

申请日：1985-01-05

Applicant: INTEL CORP

Inventor： FARRELL ROBERT LELAND ,  SARABI ALIREZA ,  TETRICK RAYMOND SCOTT

IPC: G06F13/376 ,  G06F13/42 ,  G06F13/40 ,  H04L25/02

Abstract: The bus structure comprises both a parallel bus (35) and a series bus (37), which connect to one another data processing units (25, 26) and peripheral devices (30), jointly referred to as "stations", in order to permit the interchange of data and messages at high speed using a minimum of "handshake" events before the actual data transmission. The serial and parallel bus protocols are controlled by message control devices (44, 50), which are coupled to each participating station. A local bus (56) is coupled to processing stations (25, 26) within the system in such a way that access can be made to local memories (54) and secondary processing resources (57) without adversely affecting the data traffic via the parallel bus (35). A direct access by other bus stations to resources (54) coupled to the local bus (56) of one station is likewise controlled by the message control device (44).