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    METHOD AND SYSTEM FOR SAFE ENQUEUING OF EVENTS
    1.
    发明申请
    METHOD AND SYSTEM FOR SAFE ENQUEUING OF EVENTS 审中-公开
    安全事件的方法和系统

    公开(公告)号：WO2013006406A3

    公开(公告)日：2013-03-28

    申请号：PCT/US2012044837

    申请日：2012-06-29

    Applicant: INTEL CORP ,  FARRELL ROBERT L ,  ADL-TABATABAI ALI-REZA ,  KOKER ALTUG

    Inventor： FARRELL ROBERT L ,  ADL-TABATABAI ALI-REZA ,  KOKER ALTUG

    IPC: G06F9/06 ,  G06F9/44

    CPC classification number: G06F9/544 ,  G06F9/545

    Abstract: A method and system to facilitate a user level application executing in a first processing unit to enqueue work or task(s) safely for a second processing unit without performing any ring transition. For example, in one embodiment of the invention, the first processing unit executes one or more user level applications, where each user level application has a task to be offloaded to a second processing unit. The first processing unit signals the second processing unit to handle the task from each user level application without performing any ring transition in one embodiment of the invention.

    Abstract translation: 一种促进在第一处理单元中执行的用户级应用程序以对第二处理单元安全地排队工作或任务而不执行任何环转换的方法和系统。 例如，在本发明的一个实施例中，第一处理单元执行一个或多个用户级应用，其中每个用户级应用具有卸载到第二处理单元的任务。 在本发明的一个实施例中，第一处理单元用信号通知第二处理单元来处理来自每个用户级应用的任务而不执行任何环转移。

    7.
    发明专利
    未知

    公开(公告)号：DE4291778B4

    公开(公告)日：2005-02-10

    申请号：DE4291778

    申请日：1992-06-04

    Applicant: INTEL CORP

    Inventor： MACWILLIAMS PETER D ,  WEBB CLAIR C ,  FARRELL ROBERT L

    IPC: G06F12/08 ,  G06F13/16 ,  G06F13/00

    Abstract: An integrated circuit, for use as a cache subsystem, implements a cache static random access memory (SRAM) storage array, a central processor unit (CPU) bus interface and a main memory bus interface. The CPU bus and main memory bus interfaces include multiplexers, buffers, and local control for optimizing burst read and write operations to and from the CPU bus. These circuits allow a full cache line to be read or written in a single access of the SRAM array. Control logic is utilized within the CPU bus interface for controlling CPU bursts in the order defined by the CPU. The memory bus interface includes internal buffers used in performing memory bus reads, write-throughs, write-backs and snoops. Tracking logic is employed for determining the appropriate internal buffer to be utilized for a particular memory bus cycle. Additionally, a data path is included for transparently passing data between the CPU and memory bus interfaces without disturbance of the SRAM array.

    8.
    发明专利
    未知

    公开(公告)号：DE4218003C2

    公开(公告)日：1997-08-21

    申请号：DE4218003

    申请日：1992-06-01

    Applicant: INTEL CORP

    Inventor： MACWILLIAMS PETER D ,  FARRELL ROBERT L ,  GOLBERT ADALBERTO ,  SILAS ITZIK

    IPC: G06F12/08

    Abstract: A second level cache memory controller, implemented as an integrated circuit unit, operates in conjunction with a secondary random access cache memory and a main memory (system) bus controller to form a second level cache memory subsystem. The subsystem is interfaced to the local processor (CPU) bus and to the main memory bus providing independent access by both buses, thereby reducing traffic of the main memory bus when the data required by the CPU is located in secondary cache. Similarly, CPU bus traffic is minimized when secondary cache access by the main memory bus for snoops and write-backs to main memory. Snoop latches interfaced with the main memory bus provide snoop access to the cache memory via the cache directory in the secondary cache controller unit. The controller also supports parallel look-up in the controller tag array and the secondary cache using most-recently-used (MRU) main memory write-through and pipelining of memory bus cycle requests.

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