公开(公告)号：AT459047T

公开(公告)日：2010-03-15

申请号：AT08251110

申请日：2008-03-27

Applicant: INTEL CORP

Inventor： YAMADA KOICHI ,  COVELLI DOUGLAS ,  VARGAS JOSE ,  KUMAR MOHAN

IPC: G06F11/20

Abstract: In a method for switching to a spare processor during runtime, a processing system determines that execution should be migrated off of an active processor. An operating system (OS) scheduler and at least one device are then paused, and the active processor is put into an idle state. State data from writable and substantially non-writable stores in the active processor is loaded into the spare processor. Interrupt routing table logic for the processing system is dynamically reprogrammed to direct external interrupts to the spare processor. The active processor may then be off-lined, and the device and OS scheduler may be unpaused or resumed. Threads may then be dispatched to the spare processor for execution. Other embodiments are described and claimed.

公开(公告)号：DE602008000690D1

公开(公告)日：2010-04-08

申请号：DE602008000690

申请日：2008-03-27

Applicant: INTEL CORP

Inventor： YAMADA KOICHI ,  COVELLI DOUGLAS ,  VARGAS JOSE ,  KUMAR MOHAN

IPC: G06F11/20

Abstract: In a method for switching to a spare processor during runtime, a processing system determines that execution should be migrated off of an active processor. An operating system (OS) scheduler and at least one device are then paused, and the active processor is put into an idle state. State data from writable and substantially non-writable stores in the active processor is loaded into the spare processor. Interrupt routing table logic for the processing system is dynamically reprogrammed to direct external interrupts to the spare processor. The active processor may then be off-lined, and the device and OS scheduler may be unpaused or resumed. Threads may then be dispatched to the spare processor for execution. Other embodiments are described and claimed.

公开(公告)号：AT374971T

公开(公告)日：2007-10-15

申请号：AT02753534

申请日：2002-08-23

Applicant: INTEL CORP

Inventor： AJANOVIC JASMIN ,  HARRIMAN DAVID ,  CAMPBELL RANDOLPH ,  VARGAS JOSE ,  HALL CLIFFORD ,  SETHI PRASHANT ,  PAWLOWSKI STEVE

IPC: G06F13/12 ,  G06F3/00 ,  G06F13/00 ,  G06F13/14 ,  G06F13/24 ,  H04L1/18 ,  H04L47/30

Abstract: A storage device is provided to maintain a count of flow control credits to be granted to a device in association with transactions over a channel to be implemented on a data link and control logic is provided to communicate, to the device, an indication of an amount of flow control credits for the device in association with a reset of the data link.