公开(公告)号：WO03058717A2

公开(公告)日：2003-07-17

申请号：PCT/US0239480

申请日：2002-12-10

Applicant: INTEL CORP

Inventor： WALK MICHAEL ,  RABADAM ELEANOR ,  KESER MILAN

IPC: H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L27/112 ,  H05K1/02 ,  H05K1/18

CPC classification number: H01L23/3128 ,  H01L23/13 ,  H01L23/49816 ,  H01L27/112 ,  H01L2224/48227 ,  H01L2924/15153 ,  H01L2924/15159 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19106 ,  H05K1/023 ,  H05K1/182

Abstract: Briefly, in accordance with one embodiment of the invention, a memory device package includes an integrated circuit die having a memory array and at least one passive component mounted to a substrate. In alternative embodiments, an array of solder balls may be mounted around the passive component.

Abstract translation: 简而言之，根据本发明的一个实施例，存储器件封装包括具有存储器阵列和安装到衬底的至少一个无源部件的集成电路管芯。 在替代实施例中，可以围绕无源部件安装焊球阵列。

公开(公告)号：WO0203463A3

公开(公告)日：2003-09-04

申请号：PCT/US0119225

申请日：2001-06-14

Applicant: INTEL CORP ,  VRTIS JOAN ,  FIGUEROA DAVID ,  KOHMURA TOSHIMI ,  WALK MICHAEL ,  HALE AARON

Inventor： VRTIS JOAN ,  FIGUEROA DAVID ,  KOHMURA TOSHIMI ,  WALK MICHAEL ,  HALE AARON

IPC: H01L23/498 ,  H01L23/50 ,  H01L23/64

CPC classification number: H01L23/50 ,  H01L23/49822 ,  H01L23/642 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/04941 ,  H01L2924/10253 ,  H01L2924/15311 ,  Y10T29/4913 ,  H01L2924/00 ,  H01L2224/0401

Abstract: An electronic package (302, Figure 3) includes one or more capacitors (308) embedded within one or more layers (310) of the package. The embedded capacitors are discrete devices, such as integrated circuit capacitors (Figures 17-18) or ceramic capacitors. During the package build-up process, the capacitors are mounted (410, Figure 4) to a package layer, and a non-conductive layer is applied (412) over the capacitors. When the build-up process is completed, the capacitor's terminals (604, 608, Figure 6) are electrically connected to the top surface of the package. The embedded capacitor structure can be used in an integrated circuit package (1904, Figure 19), an interposer (1906), and/or a printed circuit board (1908).

Abstract translation: 电子封装（302，图3）包括嵌入在封装的一个或多个层（310）内的一个或多个电容器（308）。 嵌入式电容器是分立器件，如集成电路电容器（图17-18）或陶瓷电容器。 在封装堆积过程中，将电容器（410，图4）安装到封装层，并且在电容器上施加非导电层（412）。 当积聚过程完成时，电容器的端子（604,608，图6）电连接到封装的顶表面。 嵌入式电容器结构可以用于集成电路封装（1904，图19），插入器（1906）和/或印刷电路板（1908）中。

公开(公告)号：AT441940T

公开(公告)日：2009-09-15

申请号：AT01944544

申请日：2001-06-14

Applicant: INTEL CORP

Inventor： VRTIS JOAN ,  FIGUEROA DAVID ,  KOHMURA TOSHIMI ,  WALK MICHAEL ,  HALE AARON

IPC: H01L23/498 ,  H01L23/50 ,  H01L23/64

Abstract: An electronic package (302, FIG. 3) includes one or more capacitors (308) embedded within one or more layers (310) of the package. The embedded capacitors are discrete devices, such as integrated circuit capacitors (FIGS. 17-18) or ceramic capacitors. During the package build-up process, the capacitors are mounted (410, FIG. 4) to a package layer, and a non-conductive layer is applied (412) over the capacitors. When the build-up process is completed, the capacitor's terminals (604, 608, FIG. 6) are electrically connected to the top surface of the package. The embedded capacitor structure can be used in an integrated circuit package (1904, FIG. 19), an interposer (1906), and/or a printed circuit board (1908).

公开(公告)号：MY126682A

公开(公告)日：2006-10-31

申请号：MYPI20012874

申请日：2001-06-19

Applicant: INTEL CORP

Inventor： HALE AARON DEAN ,  WALK MICHAEL ,  DAVID G FIGUEROA ,  VRTIS JOAN K ,  KOHMURA TOSHIMI

IPC: H05K1/18 ,  H01L23/498 ,  H01L23/50 ,  H01L23/64

Abstract: AN ELECTRONIC PACKAGE (302, FIGURE 3) INCLUDES ONE OR MORE CAPACITORS (308) EMBEDDED WITHIN ONE OR MORE LAYERS (310) OF THE PACKAGE. THE EMBEDDED CAPACITORS ARE DISCRETE DEVICES, SUCH AS INTEGRATED CIRCUIT CAPACITORS (FIGURE 17-18) OR CERAMIC CAPACITORS. DURING THE PACKAGE BUILD-UP PROCESS, THE CAPACITORS ARE MOUNTED (410, FIGURE 4) TO A PACKAGE LAYER, AND A NON-CONDUCTIVE LAYER IS APPLIED (412) OVER THE CAPACITORS. WHEN THE BUILD-UP PROCESS IS COMPLETED , THE CAPACITOR'S TERMINALS (604,608, FIGURE 6) ARE ELECTRICALLY CONNECTED TO THE TOP SURFACE OF THE PACKAGE. THE EMBEDDED CAPACITOR STRUCTURE CAN BE USED IN AN INTEGRATED CIRCUIT PACKAGE (1904, FIGURE 19), AN INTERPOSER (1906), AND /OR A PRINTED CIRCUIT BOARD (1908).(FIG 10)

公开(公告)号：AU2003225932A1

公开(公告)日：2003-10-20

申请号：AU2003225932

申请日：2003-03-21

Applicant: INTEL CORP

Inventor： WALK MICHAEL ,  COOMER BOYD

IPC: H01L21/48 ,  H05K3/10 ,  H05K3/38 ,  H05K3/44 ,  H05K3/46

Abstract: Adhesive material is applied to a surface of a metallic core layer. The adhesive material is removed from a conductive region of the metallic core layer. A metallic contact is provided over the conductive region of the metallic core layer. The metallic core layer is laminated to an imprinted buildup layer, the buildup layer having a dielectric region and a conductive region, wherein a nonconductive region of the metallic core layer is bonded to the dielectric region of the buildup layer and the conductive region of the metallic core layer is bonded to the conductive region of the imprinted-buildup layer.

公开(公告)号：MY124519A

公开(公告)日：2006-06-30

申请号：MYPI20015487

申请日：2001-12-03

Applicant: INTEL CORP

Inventor： WALK MICHAEL ,  FIGUEROA DAVID G ,  DO HUONG T ,  RODRIGUEZ JORGE PEDRO

IPC: H01G2/20 ,  H01G20060101 ,  H01G4/252 ,  H01G2/00 ,  H01G2/06 ,  H01G4/228 ,  H01L23/52

Abstract: A CAPACITOR (FIGS. 6-9) INCLUDES ONE OR MORE EXTENDED SURFACE LANDS (604, 704, 804, 904, FIGS. 6-9). IN ONE EMBODIMENT, EACH EXTENDED SURFACE LAND IS A LAND ON A TOP OR BOTTOM SURFACE OF THE CAPACITOR HAVING A LAND LENGTH THAT IS EQUAL TO AT LEAST 30% OF THE WIDTH (614, FIG. 6) OF THE CAPACITOR OR 20% OF THE LENGTH (914, FIG. 9) OF THE CAPACITOR. WHEN EMBEDDED WITHIN AN INTEGRATED CIRCUIT PACKAGE (1102, FIG 11.), TWO OR MORE VIAS (1112) CAN BE ELECTRICALLY CONNECTED TO THE EXTENDED SURFACE LANDS (1108).(FIGURE 6)

公开(公告)号：HK1058433A1

公开(公告)日：2004-05-14

申请号：HK04101090

申请日：2004-02-16

Applicant: INTEL CORP

Inventor： VRTIS JOAN ,  FIGUEROA DAVID ,  KOHMURA TOSHIMI ,  WALK MICHAEL ,  HALE AARON

IPC: H01L20090101 ,  H01L23/498 ,  H01L23/50 ,  H01L23/64

Abstract: An electronic package (302, FIG. 3) includes one or more capacitors (308) embedded within one or more layers (310) of the package. The embedded capacitors are discrete devices, such as integrated circuit capacitors (FIGS. 17-18) or ceramic capacitors. During the package build-up process, the capacitors are mounted (410, FIG. 4) to a package layer, and a non-conductive layer is applied (412) over the capacitors. When the build-up process is completed, the capacitor's terminals (604, 608, FIG. 6) are electrically connected to the top surface of the package. The embedded capacitor structure can be used in an integrated circuit package (1904, FIG. 19), an interposer (1906), and/or a printed circuit board (1908).

公开(公告)号：AU6694401A

公开(公告)日：2002-01-14

申请号：AU6694401

申请日：2001-06-14

Applicant: INTEL CORP

Inventor： VRTIS JOAN ,  FIGUEROA DAVID ,  KOHMURA TOSHIMI ,  WALK MICHAEL ,  HALE AARON

IPC: H01L23/498 ,  H01L23/50 ,  H01L23/64

Abstract: An electronic package (302, FIG. 3) includes one or more capacitors (308) embedded within one or more layers (310) of the package. The embedded capacitors are discrete devices, such as integrated circuit capacitors (FIGS. 17-18) or ceramic capacitors. During the package build-up process, the capacitors are mounted (410, FIG. 4) to a package layer, and a non-conductive layer is applied (412) over the capacitors. When the build-up process is completed, the capacitor's terminals (604, 608, FIG. 6) are electrically connected to the top surface of the package. The embedded capacitor structure can be used in an integrated circuit package (1904, FIG. 19), an interposer (1906), and/or a printed circuit board (1908).

公开(公告)号：DE60333084D1

公开(公告)日：2010-08-05

申请号：DE60333084

申请日：2003-03-21

Applicant: INTEL CORP

Inventor： COOMER BOYD ,  WALK MICHAEL

IPC: H05K3/46 ,  H01L21/48 ,  H05K3/10 ,  H05K3/38 ,  H05K3/44

公开(公告)号：AT472242T

公开(公告)日：2010-07-15

申请号：AT03746044

申请日：2003-03-21

Applicant: INTEL CORP

Inventor： COOMER BOYD ,  WALK MICHAEL

IPC: H05K3/46 ,  H01L21/48 ,  H05K3/10 ,  H05K3/38 ,  H05K3/44

Abstract: Adhesive material is applied to a surface of a metallic core layer. The adhesive material is removed from a conductive region of the metallic core layer. A metallic contact is provided over the conductive region of the metallic core layer. The metallic core layer is laminated to an imprinted buildup layer, the buildup layer having a dielectric region and a conductive region, wherein a nonconductive region of the metallic core layer is bonded to the dielectric region of the buildup layer and the conductive region of the metallic core layer is bonded to the conductive region of the imprinted-buildup layer.