公开(公告)号：JP2009165120A

公开(公告)日：2009-07-23

申请号：JP2008322188

申请日：2008-12-18

Applicant: Intel Corp ,  インテル コーポレイション

Inventor： ELGOUSI MUHAMMED ,  KAR JAYASHREE ,  FIGUEROA DAVID ,  VENKATARAMAN SRIKRISHNAN

IPC: H03K19/003 ,  H03K5/1252 ,  H03K19/00

CPC classification number: G06F1/26 ,  G06F13/4022

Abstract: PROBLEM TO BE SOLVED: To reduce a noise by implementing a port-to-port delay. SOLUTION: A noise reduction method comprises: determining a frequency of a greatest noise on a high-speed data link when turning on a power delivery network; determining a delay time between a first port and a second port that minimizes the greatest noise; and turning on the second port after the delay time from turning on the first port. Other embodiments are also disclosed and claimed. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：通过实现端口到端口延迟来减少噪声。 解决方案：降噪方法包括：当打开供电网络时，确定高速数据链路上最大噪声的频率; 确定使最大噪声最小化的第一端口和第二端口之间的延迟时间; 并在延迟时间之后打开第二个端口打开第一个端口。 还公开并要求保护其他实施例。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：WO2005001928A3

公开(公告)日：2005-06-09

申请号：PCT/US2004018091

申请日：2004-06-03

Applicant: INTEL CORP

Inventor： HESTER JENNIFER ,  LI YUAN-LIANG ,  DESMITH MICHAEL ,  FIGUEROA DAVID ,  ZHONG DONG

IPC: H01G4/38 ,  H01L23/498 ,  H01L23/64 ,  H05K1/02 ,  H05K1/11 ,  H04B3/32 ,  H04B3/28 ,  H05K1/16

CPC classification number: H05K1/114 ,  H01G4/385 ,  H01L23/49838 ,  H01L23/642 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01021 ,  H01L2924/01057 ,  H01L2924/15312 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K2201/09263 ,  H05K2201/09345 ,  H05K2201/0979 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2224/0401

Abstract: According to some embodiments, a device includes a first conductive plane electrically coupled to a first terminal associated with a first polarity and a second terminal associated with the first polarity, a second conductive plane electrically coupled to a third terminal associated with a second polarity, and a dielectric disposed between the first conductive plane and the second conductive; plane. A first capacitance is present between the first terminal and the third terminal, a second capacitance is present between the second terminal and the third terminal, and the first capacitance and the second capacitance may be substantially dissimilar.

Abstract translation: 根据一些实施例，一种装置包括电耦合到与第一极性关联的第一端子和与第一极性关联的第二端子的第一导电平面，电耦合到与第二极性关联的第三端子的第二导电平面，以及 布置在所述第一导电平面和所述第二导电之间的电介质; 平面。 在第一端子和第三端子之间存在第一电容，在第二端子和第三端子之间存在第二电容，并且第一电容和第二电容可以基本不相似。

公开(公告)号：WO0250852A2

公开(公告)日：2002-06-27

申请号：PCT/US0144822

申请日：2001-11-27

Applicant: INTEL CORP ,  FIGUEROA DAVID ,  WALK MICHAEL J ,  RODRIGUEZ JORGE P ,  DO HUONG

Inventor： FIGUEROA DAVID ,  WALK MICHAEL J ,  RODRIGUEZ JORGE P ,  DO HUONG

IPC: H01G4/252 ,  H01G20060101 ,  H01G2/00 ,  H01G2/06 ,  H01G2/20 ,  H01G4/228 ,  H01L23/52 ,  H01G

CPC classification number: H01G2/065 ,  H01L2924/15311

Abstract: A capacitor (Figures 6-9) includes one or more extended surface lands (604, 704, 804, 904, Figures 6-9). In one embodiment, each extended surface land is a land on a top or bottom surface of the capacitor, having a land length that is equal to at least 30% of the width (614, Figure 6) of the capacitor or 20% of the length (914, figure 9) of the capacitor. When embedded within an integrated circuit package (1102, Figure 11), two or more vias (1112) can be electrically connected to the extended surface lands (1108).

Abstract translation: 电容器（图6-9）包括一个或多个延伸的表面焊盘（604,704,804,904，图6-9）。 在一个实施例中，每个延伸表面焊盘是在电容器的顶部或底部表面上的焊盘，其具有等于电容器的宽度（图6的614）或者电容器的宽度的至少30％的20％ 长度（914，图9）。 当嵌入集成电路封装（1102，图11）中时，两个或更多个通孔（1112）可以电连接到扩展表面焊盘（1108）。

公开(公告)号：WO0203463A3

公开(公告)日：2003-09-04

申请号：PCT/US0119225

申请日：2001-06-14

Applicant: INTEL CORP ,  VRTIS JOAN ,  FIGUEROA DAVID ,  KOHMURA TOSHIMI ,  WALK MICHAEL ,  HALE AARON

Inventor： VRTIS JOAN ,  FIGUEROA DAVID ,  KOHMURA TOSHIMI ,  WALK MICHAEL ,  HALE AARON

IPC: H01L23/498 ,  H01L23/50 ,  H01L23/64

CPC classification number: H01L23/50 ,  H01L23/49822 ,  H01L23/642 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/04941 ,  H01L2924/10253 ,  H01L2924/15311 ,  Y10T29/4913 ,  H01L2924/00 ,  H01L2224/0401

Abstract: An electronic package (302, Figure 3) includes one or more capacitors (308) embedded within one or more layers (310) of the package. The embedded capacitors are discrete devices, such as integrated circuit capacitors (Figures 17-18) or ceramic capacitors. During the package build-up process, the capacitors are mounted (410, Figure 4) to a package layer, and a non-conductive layer is applied (412) over the capacitors. When the build-up process is completed, the capacitor's terminals (604, 608, Figure 6) are electrically connected to the top surface of the package. The embedded capacitor structure can be used in an integrated circuit package (1904, Figure 19), an interposer (1906), and/or a printed circuit board (1908).

Abstract translation: 电子封装（302，图3）包括嵌入在封装的一个或多个层（310）内的一个或多个电容器（308）。 嵌入式电容器是分立器件，如集成电路电容器（图17-18）或陶瓷电容器。 在封装堆积过程中，将电容器（410，图4）安装到封装层，并且在电容器上施加非导电层（412）。 当积聚过程完成时，电容器的端子（604,608，图6）电连接到封装的顶表面。 嵌入式电容器结构可以用于集成电路封装（1904，图19），插入器（1906）和/或印刷电路板（1908）中。

公开(公告)号：DE10392992T5

公开(公告)日：2005-07-21

申请号：DE10392992

申请日：2003-07-25

Applicant: INTEL CORP

Inventor： BALDWIN CHRIS ,  FIGUEROA DAVID ,  LI YUAN-LIANG ,  YAHYAEI-MOAYYED FARZANEH ,  ZHONG DONG ,  HE JIANGGI

IPC: H01L23/498 ,  H01L23/50 ,  H01L23/00

Abstract: An integrated circuit including a die, a power terminal and a ground terminal all mounted onto a substrate. The power terminal including a body and a first extension projecting from the body, and the ground terminal including a body and a second extension projecting from the body. The second extension on the ground terminal being adjacent to the first extension on the power terminal to offset inductance that is generated by supplying current to the die through the power terminal.

公开(公告)号：AU2003263817A8

公开(公告)日：2004-02-16

申请号：AU2003263817

申请日：2003-07-25

Applicant: INTEL CORP

Inventor： HE JIANGGI ,  FIGUEROA DAVID ,  ZHONG DONG ,  BALDWIN CHRIS ,  LI YUAN-LIANG ,  YAHYAEI-MOAYYED FARZANEH

IPC: H01L23/498 ,  H01L23/50

Abstract: An integrated circuit including a die, a power terminal and a ground terminal all mounted onto a substrate. The power terminal including a body and a first extension projecting from the body, and the ground terminal including a body and a second extension projecting from the body. The second extension on the ground terminal being adjacent to the first extension on the power terminal to offset inductance that is generated by supplying current to the die through the power terminal.

公开(公告)号：WO2004012261A2

公开(公告)日：2004-02-05

申请号：PCT/US0323375

申请日：2003-07-25

Applicant: INTEL CORP

Inventor： ZHONG DONG ,  YAHYAEI-MOAYYED FARZANEH ,  FIGUEROA DAVID ,  BALDWIN CHRIS ,  HE JIANGGI ,  LI YUAN-LIANG

IPC: H01L23/498 ,  H01L23/50 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An integrated circuit including a die, a power terminal and a ground terminal all mounted onto a substrate. The power terminal including a body and a first extension projecting from the body, and the ground terminal including a body and a second extension projecting from the body. The second extension on the ground terminal being adjacent to the first extension on the power terminal to offset inductance that is generated by supplying current to the die through the power terminal.

Abstract translation: 集成电路包括全部安装到衬底上的管芯，电源端子和接地端子。 电源端子包括主体和从主体突出的第一延伸部，并且接地端子包括主体和从主体突出的第二延伸部。 接地端子上的第二延伸部分与电源端子上的第一延伸部分相邻以抵消通过电源端子向管芯提供电流而产生的电感。

公开(公告)号：WO0219430A2

公开(公告)日：2002-03-07

申请号：PCT/US0126822

申请日：2001-08-29

Applicant: INTEL CORP

Inventor： WERMER PAUL ,  FIGUEROA DAVID ,  CHAKRAVORTY KISHORE ,  GUPTA DEBABRATA

IPC: H01L23/498 ,  H01L23/50 ,  H05K1/03 ,  H05K1/14 ,  H05K1/16 ,  H05K3/46 ,  H01L27/00

CPC classification number: H01L23/49822 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/15174 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/0306 ,  H05K1/141 ,  H05K1/162 ,  H05K1/185 ,  H05K3/4605 ,  H05K3/4688 ,  H05K2201/0154 ,  H05K2201/09309 ,  H05K2201/10674 ,  H01L2224/0401

Abstract: To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one embedded capacitor in a multilayer ceramic/organic hybrid substrate. In one embodiment, a ceramic portion of the substrate includes at least one capacitor formed of a high permittivity layer sandwiched between conductive planes. An organic portion of the substrate includes suitable routing and fan-out of power and signal conductors. The organic portion includes a build-up of multiple layers of organic material overlying the ceramic portion. Also described are an electronic system, a data processing system, and various methods of manufacture.

Abstract translation: 为了降低开关噪声，集成电路管芯的电源端子耦合到多层陶瓷/有机混合衬底中的至少一个嵌入式电容器的相应端子。 在一个实施例中，衬底的陶瓷部分包括由夹在导电平面之间的高电容率层形成的至少一个电容器。 基板的有机部分包括电源和信号导体的合适布线和扇出。 有机部分包括覆盖陶瓷部分的多层有机材料的堆积。 还描述了电子系统，数据处理系统和各种制造方法。

公开(公告)号：DE10392992B4

公开(公告)日：2017-03-02

申请号：DE10392992

申请日：2003-07-25

Applicant: INTEL CORP

Inventor： BALDWIN CHRIS ,  FIGUEROA DAVID ,  LI YUAN-LIANG ,  YAHYAEI-MOAYYED FARZANEH ,  ZHONG DONG ,  HE JIANGGI

IPC: H01L23/498 ,  H01L23/50

Abstract: Integrierte Schaltung, mit: – einem Substrat (12); – einem auf dem Substrat (12) angebrachten Chip (11); – einem ersten, auf dem Substrat (12) angebrachten und elektrisch mit dem Chip (11) verbundenen Versorgungsanschluß (14A; 34; 54), wobei der erste Versorgungsanschluß (14A; 34; 54) einen Hauptteil (15; 35; 55) und einen ersten Vorsprung (16; 36; 56), der von dem Hauptteil (15; 35; 55) vorsteht, aufweist; und – einem ersten, auf dem Substrat (12) angebrachten und elektrisch mit dem Chip (11) verbundenen Erdungsanschluß (24A; 44; 64), wobei der erste Erdungsanschluß (24A; 44; 64) einen Hauptteil (25; 45; 65) und einen zweiten Vorsprung (26; 46; 66), der von dem Hauptteil (25; 45; 65) vorsteht, aufweist, wobei der zweite Vorsprung (26; 46; 66) an dem ersten Erdungsanschluß (24A; 44; 64) neben dem ersten Vorsprung (16; 36; 56) an dem ersten Versorgungsanschluß (14A; 34; 54) liegt, dadurch gekennzeichnet, dass der erste Versorgungsanschluß (14A; 34; 54) und der erste Erdungsanschluß (24A; 44; 64) planar auf der Rückseite (13A) des Substrats (12) und der Chip (11) auf der Vorderseite (13B) des Substrats (12) angeordnet sind.

公开(公告)号：AT441940T

公开(公告)日：2009-09-15

申请号：AT01944544

申请日：2001-06-14

Applicant: INTEL CORP

Inventor： VRTIS JOAN ,  FIGUEROA DAVID ,  KOHMURA TOSHIMI ,  WALK MICHAEL ,  HALE AARON

IPC: H01L23/498 ,  H01L23/50 ,  H01L23/64

Abstract: An electronic package (302, FIG. 3) includes one or more capacitors (308) embedded within one or more layers (310) of the package. The embedded capacitors are discrete devices, such as integrated circuit capacitors (FIGS. 17-18) or ceramic capacitors. During the package build-up process, the capacitors are mounted (410, FIG. 4) to a package layer, and a non-conductive layer is applied (412) over the capacitors. When the build-up process is completed, the capacitor's terminals (604, 608, FIG. 6) are electrically connected to the top surface of the package. The embedded capacitor structure can be used in an integrated circuit package (1904, FIG. 19), an interposer (1906), and/or a printed circuit board (1908).