公开(公告)号：DE112016005919T5

公开(公告)日：2018-09-13

申请号：DE112016005919

申请日：2016-12-14

Applicant: INTEL CORP

Inventor： SHANBHOGUE VEDVYAS ,  BRYANT CHRISTOPHER ,  WIEDEMEIER JEFF

IPC: G06F12/14

Abstract: Eine Vorrichtung und ein Verfahren zum Schutz von Sub-Seiten von erweiterten Seitentabellen. Zum Beispiel umfasst eine Ausführungsform einer Vorrichtung: einen Seiten-Fehlschlag-Handhaber zum Durchführen eines Seitenlaufs unter Verwendung einer physikalischen Gastadresse (GPA) und zum Erkennen, ob eine mit der GPA identifizierte Seite mit Sub-Seiten-Berechtigungen abgebildet ist; einen Sub-Seiten-Steuerspeicher zum Speichern mindestens einer GPA und anderer Sub-Seitebezogener Daten; wobei der Seiten-Fehlschlag-Handhaber vorgesehen ist, um zu bestimmen, ob die GPA in dem Sub-Seiten-Steuerspeicher programmiert ist; und der Seiten-Fehlschlag-Handhaber vorgesehen ist, eine Übersetzung an einen Adressenübersetzungspuffer (TLB) mit einer Sub-Seiten-Schutzangabe zu senden, die eingestellt ist, um eine Übereinstimmung der Sub-Seiten-bezogenen Daten zu bewirken, wenn ein TLB-Treffer vorliegt.

公开(公告)号：WO2012040545A9

公开(公告)日：2012-10-04

申请号：PCT/US2011052899

申请日：2011-09-23

Applicant: INTEL CORP ,  WIEDEMEIER JEFF ,  SAMUDRALA SRIDHAR ,  GOLLIVER ROGER

Inventor： WIEDEMEIER JEFF ,  SAMUDRALA SRIDHAR ,  GOLLIVER ROGER

IPC: G06F15/76 ,  G06F7/00 ,  G06F9/30

CPC classification number: G06F7/483 ,  G06F7/5443 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30036

Abstract: A vector functional unit implemented on a semiconductor chip to perform vector operations of dimension N is described. The vector functional unit includes N functional units. Each of the N functional units have logic circuitry to perform: a first integer multiply add instruction that presents highest ordered bits but not lowest ordered bits of a first integer multiply add calculation, and, a second integer multiply add instruction that presents lowest ordered bits but not highest ordered bits of a second integer multiply add calculation.

公开(公告)号：BR112013008616A2

公开(公告)日：2016-06-14

申请号：BR112013008616

申请日：2011-09-23

Applicant: INTEL CORP

Inventor： MAHURIN ERIC W ,  WIEDEMEIER JEFF ,  GOLLIVER ROGER ,  SAMUDRALA SRIDHAR

IPC: G06F9/30 ,  G06F7/00 ,  G06F15/76

公开(公告)号：DE112011103195T5

公开(公告)日：2013-06-27

申请号：DE112011103195

申请日：2011-09-23

Applicant: INTEL CORP

Inventor： WIEDEMEIER JEFF ,  SAMUDRALA SRIDHAR ,  GOLLIVER ROGER ,  MAHURIN ERIC W

IPC: G06F15/76 ,  G06F7/00 ,  G06F9/30

Abstract: Es wird ein Verfahren zum Ausführen von Vektoroperationen auf einem Halbleiterchip beschrieben. Das Verfahren umfasst das Ausführen einer ersten Vektoranweisung mit einer Vektor-Funktionseinheit, die auf dem Halbleiterchip implementiert ist, und das Ausführen einer zweiten Vektoranweisung mit der Vektor-Funktionseinheit. Die erste Vektoranweisung ist eine Multiply-Add-Vektoranweisung. Die zweite Vektoranweisung ist eine Vektoranweisung zum Zählen von führenden Nullen.

公开(公告)号：GB2498466A

公开(公告)日：2013-07-17

申请号：GB201304303

申请日：2011-09-24

Applicant: INTEL CORP

Inventor： WIEDEMEIER JEFF ,  SAMUDRALA SRIDHAR ,  GOLLIVER ROGER A

IPC: G06F15/76 ,  G06F7/76 ,  G06F9/305

Abstract: A semiconductor processor is described. The semiconductor processor includes logic circuitry to perform a logical reduction instruction. The logic circuitry has swizzle circuitry to swizzle a vector's elements so as to form a swizzle vector. The logic circuitry also has vector logic circuitry to perform a vector logic operation on said vector and said swizzle vector.

公开(公告)号：GB2497450A

公开(公告)日：2013-06-12

申请号：GB201303473

申请日：2011-09-23

Applicant: INTEL CORP

Inventor： WIEDEMEIER JEFF ,  SAMUDRALA SRIDHAR ,  GOLLIVER ROGER A

IPC: G06F9/30 ,  G06F7/483

Abstract: A vector functional unit implemented on a semiconductor chip to perform vector operations of dimension N is described. The vector functional unit includes N functional units. Each of the N functional units have logic circuitry to perform: a first integer multiply add instruction that presents highest ordered bits but not lowest ordered bits of a first integer multiply add calculation, and, a second integer multiply add instruction that presents lowest ordered bits but not highest ordered bits of a second integer multiply add calculation.

公开(公告)号：WO2012040665A3

公开(公告)日：2012-07-26

申请号：PCT/US2011053153

申请日：2011-09-24

Applicant: INTEL CORP ,  WIEDEMEIER JEFF ,  SAMUDRALA SRIDHAR ,  GOLLIVER ROGER

Inventor： WIEDEMEIER JEFF ,  SAMUDRALA SRIDHAR ,  GOLLIVER ROGER

IPC: G06F9/305 ,  G06F1/00 ,  G06F9/30 ,  G06F9/44

CPC classification number: G06F9/30029 ,  G06F7/00 ,  G06F9/06 ,  G06F9/30032 ,  G06F9/30036 ,  G06F15/76

Abstract: A semiconductor processor is described. The semiconductor processor includes logic circuitry to perform a logical reduction instruction. The logic circuitry has swizzle circuitry to swizzle a vector's elements so as to form a swizzle vector. The logic circuitry also has vector logic circuitry to perform a vector logic operation on said vector and said swizzle vector.

Abstract translation: 描述半导体处理器。 半导体处理器包括执行逻辑减少指令的逻辑电路。 逻辑电路具有旋转矢量元件的旋转电路，以便形成旋转矢量。 逻辑电路还具有矢量逻辑电路，用于对所述矢量和所述旋转矢量执行矢量逻辑运算。

公开(公告)号：WO2012040545A2

公开(公告)日：2012-03-29

申请号：PCT/US2011052899

申请日：2011-09-23

Applicant: INTEL CORP ,  WIEDEMEIER JEFF ,  SAMUDRALA SRIDHAR ,  GOLLIVER ROGER

Inventor： WIEDEMEIER JEFF ,  SAMUDRALA SRIDHAR ,  GOLLIVER ROGER

IPC: G06F15/76 ,  G06F7/00 ,  G06F9/30

CPC classification number: G06F7/483 ,  G06F7/5443 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30036

Abstract: A vector functional unit implemented on a semiconductor chip to perform vector operations of dimension N is described. The vector functional unit includes N functional units. Each of the N functional units have logic circuitry to perform: a first integer multiply add instruction that presents highest ordered bits but not lowest ordered bits of a first integer multiply add calculation, and, a second integer multiply add instruction that presents lowest ordered bits but not highest ordered bits of a second integer multiply add calculation.

Abstract translation: 描述在半导体芯片上实现的用于执行维度N的矢量运算的矢量功能单元。 矢量功能单元包括N个功能单元。 N个功能单元中的每一个具有执行以下操作的逻辑电路：第一整数乘加指令，其呈现最高有序位但不是第一整数乘加计算的最低有序位;以及第二整数乘加指令，其呈现最低有序位，但是 而不是第二整数乘加计算的最高有序位。

公开(公告)号：WO2012135429A3

公开(公告)日：2012-12-27

申请号：PCT/US2012031093

申请日：2012-03-29

Applicant: INTEL CORP ,  KOU LEIGANG ,  WIEDEMEIER JEFF ,  FILIPPO MIKE

Inventor： KOU LEIGANG ,  WIEDEMEIER JEFF ,  FILIPPO MIKE

IPC: G06F12/08 ,  G06F12/10

CPC classification number: G06F12/0862 ,  G06F9/383 ,  G06F12/0215 ,  G06F12/0864 ,  G06F2212/6026 ,  G06F2212/6028

Abstract: A method and system to optimize prefetching of cache memory lines in a processing unit. The processing unit has logic to determine whether a vector memory operand is cached in two or more adjacent cache memory lines. In one embodiment of the invention, the determination of whether the vector memory operand is cached in two or more adjacent cache memory lines is based on the size and the starting address of the vector memory operand. In one embodiment of the invention, the pre-fetching of the two or more adjacent cache memory lines that cache the vector memory operand is performed using a single instruction that uses one issue slot and one data cache memory execution slot. By doing so, it avoids additional software prefetching instructions or operations to read a single vector memory operand when the vector memory operand is cached in more than one cache memory line.

Abstract translation: 一种用于优化处理单元中的高速缓冲存储器线的预取的方法和系统。 处理单元具有确定向量存储器操作数是否被缓存在两个或更多个相邻高速缓冲存储器行中的逻辑。 在本发明的一个实施例中，矢量存储器操作数是否被缓存在两个或多个相邻高速缓存存储器线中的确定是基于向量存储器操作数的大小和起始地址。 在本发明的一个实施例中，使用使用一个问题时隙和一个数据高速缓冲存储器执行时隙的单个指令来执行缓存向量存储器操作数的两个或更多个相邻高速缓存存储器行的预取。 通过这样做，当向量存储器操作数被缓存在多于一个高速缓冲存储器行中时，避免了额外的软件预取指令或操作来读取单个向量存储器操作数。

公开(公告)号：WO2012040539A3

公开(公告)日：2012-07-05

申请号：PCT/US2011052889

申请日：2011-09-23

Applicant: INTEL CORP ,  WIEDEMEIER JEFF ,  SAMUDRALA SRIDHAR ,  GOLLIVER ROGER ,  MAHURIN ERIC W

Inventor： WIEDEMEIER JEFF ,  SAMUDRALA SRIDHAR ,  GOLLIVER ROGER ,  MAHURIN ERIC W

IPC: G06F15/76 ,  G06F7/00 ,  G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30014 ,  G06F9/30018

Abstract: A method of performing vector operations on a semiconductor chip is described. The method includes performing a first vector instruction with a vector functional unit implemented on the semiconductor chip and performing a second vector instruction with the vector functional unit. The first vector instruction is a vector multiply add instruction. The second vector instruction is a vector leading zeros count instruction.

Abstract translation: 描述了在半导体芯片上执行向量操作的方法。 该方法包括利用在半导体芯片上实现的矢量功能单元执行第一矢量指令，并用矢量功能单元执行第二矢量指令。 第一个向量指令是一个向量乘法加法指令。 第二个向量指令是向量前导零计数指令。