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公开(公告)号：WO2012040545A9
公开(公告)日：2012-10-04
申请号：PCT/US2011052899
申请日：2011-09-23
Applicant: INTEL CORP , WIEDEMEIER JEFF , SAMUDRALA SRIDHAR , GOLLIVER ROGER
Inventor： WIEDEMEIER JEFF , SAMUDRALA SRIDHAR , GOLLIVER ROGER
CPC classification number: G06F7/483 , G06F7/5443 , G06F9/30014 , G06F9/30018 , G06F9/30036
Abstract: A vector functional unit implemented on a semiconductor chip to perform vector operations of dimension N is described. The vector functional unit includes N functional units. Each of the N functional units have logic circuitry to perform: a first integer multiply add instruction that presents highest ordered bits but not lowest ordered bits of a first integer multiply add calculation, and, a second integer multiply add instruction that presents lowest ordered bits but not highest ordered bits of a second integer multiply add calculation.
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2.发明申请FUNCTIONAL UNIT FOR VECTOR LEADING ZEROES, VECTOR TRAILING ZEROES, VECTOR OPERAND 1S COUNT AND VECTOR PARITY CALCULATION 审中-公开功能单元，用于向量引导零点，矢量跟踪零，矢量运算1S计数和矢量奇偶计算
公开(公告)号：WO2012040539A3
公开(公告)日：2012-07-05
申请号：PCT/US2011052889
申请日：2011-09-23
Applicant: INTEL CORP , WIEDEMEIER JEFF , SAMUDRALA SRIDHAR , GOLLIVER ROGER , MAHURIN ERIC W
Inventor： WIEDEMEIER JEFF , SAMUDRALA SRIDHAR , GOLLIVER ROGER , MAHURIN ERIC W
CPC classification number: G06F9/30036 , G06F9/30014 , G06F9/30018
Abstract: A method of performing vector operations on a semiconductor chip is described. The method includes performing a first vector instruction with a vector functional unit implemented on the semiconductor chip and performing a second vector instruction with the vector functional unit. The first vector instruction is a vector multiply add instruction. The second vector instruction is a vector leading zeros count instruction.
Abstract translation: 描述了在半导体芯片上执行向量操作的方法。 该方法包括利用在半导体芯片上实现的矢量功能单元执行第一矢量指令，并用矢量功能单元执行第二矢量指令。 第一个向量指令是一个向量乘法加法指令。 第二个向量指令是向量前导零计数指令。
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3.发明申请
公开(公告)号：WO2012040665A3
公开(公告)日：2012-07-26
申请号：PCT/US2011053153
申请日：2011-09-24
Applicant: INTEL CORP , WIEDEMEIER JEFF , SAMUDRALA SRIDHAR , GOLLIVER ROGER
Inventor： WIEDEMEIER JEFF , SAMUDRALA SRIDHAR , GOLLIVER ROGER
CPC classification number: G06F9/30029 , G06F7/00 , G06F9/06 , G06F9/30032 , G06F9/30036 , G06F15/76
Abstract: A semiconductor processor is described. The semiconductor processor includes logic circuitry to perform a logical reduction instruction. The logic circuitry has swizzle circuitry to swizzle a vector's elements so as to form a swizzle vector. The logic circuitry also has vector logic circuitry to perform a vector logic operation on said vector and said swizzle vector.
Abstract translation: 描述半导体处理器。 半导体处理器包括执行逻辑减少指令的逻辑电路。 逻辑电路具有旋转矢量元件的旋转电路，以便形成旋转矢量。 逻辑电路还具有矢量逻辑电路，用于对所述矢量和所述旋转矢量执行矢量逻辑运算。
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公开(公告)号：WO2012040545A2
公开(公告)日：2012-03-29
申请号：PCT/US2011052899
申请日：2011-09-23
Applicant: INTEL CORP , WIEDEMEIER JEFF , SAMUDRALA SRIDHAR , GOLLIVER ROGER
Inventor： WIEDEMEIER JEFF , SAMUDRALA SRIDHAR , GOLLIVER ROGER
CPC classification number: G06F7/483 , G06F7/5443 , G06F9/30014 , G06F9/30018 , G06F9/30036
Abstract: A vector functional unit implemented on a semiconductor chip to perform vector operations of dimension N is described. The vector functional unit includes N functional units. Each of the N functional units have logic circuitry to perform: a first integer multiply add instruction that presents highest ordered bits but not lowest ordered bits of a first integer multiply add calculation, and, a second integer multiply add instruction that presents lowest ordered bits but not highest ordered bits of a second integer multiply add calculation.
Abstract translation: 描述在半导体芯片上实现的用于执行维度N的矢量运算的矢量功能单元。 矢量功能单元包括N个功能单元。 N个功能单元中的每一个具有执行以下操作的逻辑电路：第一整数乘加指令，其呈现最高有序位但不是第一整数乘加计算的最低有序位;以及第二整数乘加指令，其呈现最低有序位，但是 而不是第二整数乘加计算的最高有序位。
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公开(公告)号：DE102020114142A1
公开(公告)日：2020-12-31
申请号：DE102020114142
申请日：2020-05-27
Applicant: INTEL CORP
Inventor： VASUDEVAN ANIL , SAMUDRALA SRIDHAR , SARANGAM PARTHASARATHY , PATIL KIRAN
IPC: G06F9/48
Abstract: Technologien für Unterbrechungs-disassoziierte Warteschlangenbildung für Multi-Warteschlangen-Eingabe-/Ausgabe-Vorrichtungen umfassen ein Bestimmen, ob ein Netzwerkpaket in einer Unterbrechungs-disassoziierten Warteschlange angekommen ist, und ein Liefern des Netzwerkpakets an eine Anwendung, die durch den Rechenknoten gemanagt wird. Die Anwendung ist mit einem Anwendungs-Thread assoziiert, und die Unterbrechungs-disassoziierte Warteschlange kann in einem Polling-Modus sein. Nachfolgend kann, ansprechend auf ein Übergangsereignis, die Unterbrechungs-disassoziierte Warteschlange in einen Unterbrechungsmodus übergehen.
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Patent Agency Ranking
公开(公告)号：DE112011105818T5
公开(公告)日：2014-10-23
申请号：DE112011105818
申请日：2011-12-09
Applicant: INTEL CORP
Inventor： SANS ROGER ESPASA , SAMUDRALA SRIDHAR , SAN ADRIAN JESUS CORBAL , VALENTINE ROBERT C , DURAN SANTIAGO GALAN , WIEDEMEIER JEFFREY G , GIRKAR MILIND BABURAO , LEE VIKTOR W , FORSYTH ANDREW THOMAS
Abstract: Es werden Ausführungsformen von Systemen, Vorrichtungen und Verfahren zum Ausführen einer Expandier- und/oder Komprimieranweisung in einem Computerprozessor beschrieben. Bei bestimmten Ausführungsformen bewirkt Die Ausführung einer Expandieranweisung die Auswahl von Elementen aus einer Quelle, die spärlich in einem Ziel zu speichern sind, auf der Basis von Werten der Schreibmaske, und Speichern jedes ausgewählten Datenelements der Quelle als spärliches Datenelement in einer Zielspeicherstelle, wobei die Zielspeicherstellen jeweils Schreibmasken-Bitpositionen entsprechen, die angeben, dass das entsprechende Datenelement der Quelle zu speichern ist.
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7.发明公开VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF 审中-公开VEKTORFREUNDLICHES BEFEHLSFORMAT UND SEINEAUSFÜHRUNG
公开(公告)号：EP2695054A4
公开(公告)日：2017-05-31
申请号：EP11862801
申请日：2011-09-30
Applicant: INTEL CORP
Inventor： VALENTINE ROBERT C , SAN ADRIAN JESUS CORBAL , SANS ROGER ESPASA , CAVIN ROBERT D , TOLL BRET L , DURAN SANTIAGO GALAN , WIEDEMEIER JEFFREY G , SAMUDRALA SRIDHAR , GIRKAR MILIND BABURAO , GROCHOWSKI EDWARD THOMAS , HALL JONATHAN CANNON , BRADFORD DENNIS R , OULD-AHMED-VALL ELMOUSTAPHA , ABEL JAMES C , CHARNEY MARK , ABRAHAM SETH , SAIR SULEYMAN , FORSYTH ANDREW THOMAS , YOUNT CHARLES , WU LISA
CPC classification number: G06F9/30181 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30047 , G06F9/30145 , G06F9/30149 , G06F9/30185 , G06F9/30192 , G06F9/34
Abstract: A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.
Abstract translation: 矢量友好的指令格式及其执行。 根据本发明的一个实施例，处理器被配置为执行指令集。 该指令集包括一个矢量友好的指令格式。 矢量友好指令格式具有多个字段，包括基本操作字段，修饰符字段，扩充操作字段和数据元素宽度字段，其中第一指令格式支持不同版本的基本操作和不同扩充操作，通过放置 基础操作字段，修饰符字段，α字段，β字段和数据元素宽度字段中的不同值，并且其中可以仅将不同值中的一个置于基本操作字段，修饰符字段， 在指令流中的第一指令格式的指令的每次出现处的alpha字段，beta字段和数据元素宽度字段。
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公开(公告)号：EP2798520A4
公开(公告)日：2016-12-07
申请号：EP11878906
申请日：2011-12-29
Applicant: INTEL CORP
Inventor： MAGKLIS GRIGORIOS , CODINA JOSEP M , ZILLES CRAIG B , NEILLY MICHAEL , SAMUDRALA SRIDHAR , MARTINEZ VICENTE ALEJANDRO , XEKALAKIS POLYCHRONIS , SANCHEZ F JESUS , LUPON MARC , TOURNAVITIS GEORGIOS , GIBERT CODINA ENRIC , GOMEZ REQUENA CRISPIN , GONZALEZ ANTONIO , HYUSEINOVA MIREM , KOTSELIDIS CHRISTOS E , LATORRE FERNANDO , LOPEZ PEDRO , MADRILES CARLOS , MARCUELLO PEDRO , MARTINEZ RAUL , ORTEGA DANIEL , PAVLOU DEMOS , STAVROU KYRIAKOS A
CPC classification number: G06F9/3001 , G06F9/30032 , G06F9/30087 , G06F9/30094 , G06F9/30101 , G06F9/3842
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公开(公告)号：BR112013025409A2
公开(公告)日：2016-12-20
申请号：BR112013025409
申请日：2011-12-12
Applicant: INTEL CORP
Inventor： FORSYTH ANDREW THOMAS , TOLL BRET L , BRADFORD DENNIS R , OULD-AHMED-VALL ELMOUSTAPHA , WIEDERMEIER JEFFREY G , ADRIAN JESUS CORBAL SAN , WU LISA K , GIRKAR MILIND BABURAO , VALENTINE ROBERT C , SAMUDRALA SRIDHAR
Abstract: sistemas, aparelhos e métodos para mistura de dois operandos de fonte em destinação única usando writemask a presente invenção refere-se a concretizações de sistemas, aparelhos, e métodos para realização de uma instrução agrupada em um processador de computação. em algumas concretizações, a execução de uma instrução agrupada causa uma seleção de dados elementos por elemento dos elementos de dados dos primeiros e segundo operandos de fonte usando as posições de btye correspondentes de um writemask como um seletor entre os primeiros e segundio operandos, e armazenagem dos elementos de dados selecionados na destinação na posição correspondente na destinação.
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公开(公告)号：DE112011105122T5
公开(公告)日：2014-02-06
申请号：DE112011105122
申请日：2011-12-12
Applicant: INTEL CORP
Inventor： VALENTINE ROBERT C , WIEDEMEIER JEFFREY G , SAMUDRALA SRIDHAR , GIRKAR MILIND BABURAO , FORSYTH ANDREW THOMAS , WU LISA K , SAN ADRIAN JESUS CORBAL , OULD-AHMED-VALL ELMOUSTAPHA , BRADFORD DENNIS R , TOLL BRET L
Abstract: Ausführungsformen von Systemen, Vorrichtungen und Verfahren zum Durchführen eines Vermischungsbefehls in einem Computerprozessor werden beschrieben. In einigen Ausführungsformen veranlaßt die Ausführung eines Vermischungsbefehls eine datenelementweise Selektion von Datenelementen erster und zweiter Quelloperanden unter Verwendung der entsprechenden Bitpositionen einer Schreibmaske als ein Selektor zwischen den ersten und zweiten Operanden und Speichern der selektierten Datenelemente in dem Ziel an der entsprechenden Position in dem Ziel.
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