公开(公告)号：WO2012040545A9

公开(公告)日：2012-10-04

申请号：PCT/US2011052899

申请日：2011-09-23

Applicant: INTEL CORP ,  WIEDEMEIER JEFF ,  SAMUDRALA SRIDHAR ,  GOLLIVER ROGER

Inventor： WIEDEMEIER JEFF ,  SAMUDRALA SRIDHAR ,  GOLLIVER ROGER

IPC: G06F15/76 ,  G06F7/00 ,  G06F9/30

CPC classification number: G06F7/483 ,  G06F7/5443 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30036

Abstract: A vector functional unit implemented on a semiconductor chip to perform vector operations of dimension N is described. The vector functional unit includes N functional units. Each of the N functional units have logic circuitry to perform: a first integer multiply add instruction that presents highest ordered bits but not lowest ordered bits of a first integer multiply add calculation, and, a second integer multiply add instruction that presents lowest ordered bits but not highest ordered bits of a second integer multiply add calculation.

公开(公告)号：AU7199601A

公开(公告)日：2002-01-30

申请号：AU7199601

申请日：2001-07-13

Applicant: INTEL CORP

Inventor： GOLLIVER ROGER ,  SUTTON JAMES II ,  LIN DERRICK ,  THAKKAR SHREEKANT ,  NEIGER GILBERT ,  MCKEEN FRANCIS ,  HERBERT HOWARD ,  RENERIS KENNETH ,  ELLISON CARL

IPC: G06F12/14 ,  G06F1/00

公开(公告)号：WO2012040665A3

公开(公告)日：2012-07-26

申请号：PCT/US2011053153

申请日：2011-09-24

Applicant: INTEL CORP ,  WIEDEMEIER JEFF ,  SAMUDRALA SRIDHAR ,  GOLLIVER ROGER

Inventor： WIEDEMEIER JEFF ,  SAMUDRALA SRIDHAR ,  GOLLIVER ROGER

IPC: G06F9/305 ,  G06F1/00 ,  G06F9/30 ,  G06F9/44

CPC classification number: G06F9/30029 ,  G06F7/00 ,  G06F9/06 ,  G06F9/30032 ,  G06F9/30036 ,  G06F15/76

Abstract: A semiconductor processor is described. The semiconductor processor includes logic circuitry to perform a logical reduction instruction. The logic circuitry has swizzle circuitry to swizzle a vector's elements so as to form a swizzle vector. The logic circuitry also has vector logic circuitry to perform a vector logic operation on said vector and said swizzle vector.

Abstract translation: 描述半导体处理器。 半导体处理器包括执行逻辑减少指令的逻辑电路。 逻辑电路具有旋转矢量元件的旋转电路，以便形成旋转矢量。 逻辑电路还具有矢量逻辑电路，用于对所述矢量和所述旋转矢量执行矢量逻辑运算。

公开(公告)号：WO2012040545A2

公开(公告)日：2012-03-29

申请号：PCT/US2011052899

申请日：2011-09-23

Applicant: INTEL CORP ,  WIEDEMEIER JEFF ,  SAMUDRALA SRIDHAR ,  GOLLIVER ROGER

Inventor： WIEDEMEIER JEFF ,  SAMUDRALA SRIDHAR ,  GOLLIVER ROGER

IPC: G06F15/76 ,  G06F7/00 ,  G06F9/30

CPC classification number: G06F7/483 ,  G06F7/5443 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30036

Abstract: A vector functional unit implemented on a semiconductor chip to perform vector operations of dimension N is described. The vector functional unit includes N functional units. Each of the N functional units have logic circuitry to perform: a first integer multiply add instruction that presents highest ordered bits but not lowest ordered bits of a first integer multiply add calculation, and, a second integer multiply add instruction that presents lowest ordered bits but not highest ordered bits of a second integer multiply add calculation.

Abstract translation: 描述在半导体芯片上实现的用于执行维度N的矢量运算的矢量功能单元。 矢量功能单元包括N个功能单元。 N个功能单元中的每一个具有执行以下操作的逻辑电路：第一整数乘加指令，其呈现最高有序位但不是第一整数乘加计算的最低有序位;以及第二整数乘加指令，其呈现最低有序位，但是 而不是第二整数乘加计算的最高有序位。

公开(公告)号：WO2012040539A3

公开(公告)日：2012-07-05

申请号：PCT/US2011052889

申请日：2011-09-23

Applicant: INTEL CORP ,  WIEDEMEIER JEFF ,  SAMUDRALA SRIDHAR ,  GOLLIVER ROGER ,  MAHURIN ERIC W

Inventor： WIEDEMEIER JEFF ,  SAMUDRALA SRIDHAR ,  GOLLIVER ROGER ,  MAHURIN ERIC W

IPC: G06F15/76 ,  G06F7/00 ,  G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30014 ,  G06F9/30018

Abstract: A method of performing vector operations on a semiconductor chip is described. The method includes performing a first vector instruction with a vector functional unit implemented on the semiconductor chip and performing a second vector instruction with the vector functional unit. The first vector instruction is a vector multiply add instruction. The second vector instruction is a vector leading zeros count instruction.

Abstract translation: 描述了在半导体芯片上执行向量操作的方法。 该方法包括利用在半导体芯片上实现的矢量功能单元执行第一矢量指令，并用矢量功能单元执行第二矢量指令。 第一个向量指令是一个向量乘法加法指令。 第二个向量指令是向量前导零计数指令。

公开(公告)号：WO0206929A2

公开(公告)日：2002-01-24

申请号：PCT/US0122027

申请日：2001-07-13

Applicant: INTEL CORP

Inventor： GOLLIVER ROGER ,  SUTTON JAMES II ,  LIN DERRICK ,  THAKKAR SHREEKANT ,  NEIGER GILBERT ,  MCKEEN FRANCIS ,  HERBERT HOWARD ,  RENERIS KENNETH ,  ELLISON CARL

IPC: G06F12/14 ,  G06F1/00

CPC classification number: G06F12/1475

Abstract: The present invention provides a method, apparatus, and system for controlling memory accesses to multiple isolated memory areas in an isolated execution environment. A page manager is used to distribute a plurality of pages to a plurality of different areas of a memory, respectively. The memory is divided into non-isolated areas and isolated areas. The page manager is located in an isolated area of memory. Further, a memory ownership page table describes each page of memory and is also located in an isolated area of memory. The page manager assigns an isolated attribute to a page if the page is distributed to an isolated are of memory. On the other hand, the page manager assigns a non-isolated attribute to a page if the page is distributed to a non-isolated area of memory. The memory ownership page table records the attribute for each page. In one embodiment, a processor having a normal execution mode and an isolated execution mode generates an access transaction. The access transaction is configured using a configuration storage that contains configuration settings related to a page and access information. An access checking circuit coupled to the configuration settings and the access information and generates an access grant signal if the access transaction is valid.

Abstract translation: 本发明提供一种用于控制对隔离执行环境中的多个隔离存储器区域的存储器访问的方法，装置和系统。 页面管理器用于分别将多个页面分发到存储器的多个不同区域。 记忆分为非隔离区和隔离区。 页面管理器位于隔离区内。 此外，存储器所有权页表描述了存储器的每一页，并且还位于存储器的隔离区域中。 页面管理器将分离的属性分配给页面，如果页面分发到隔离的内存。 另一方面，如果页面被分发到存储器的非隔离区域，则页面管理器将非隔离属性分配给页面。 内存所有权页表记录每个页面的属性。 在一个实施例中，具有正常执行模式和隔离执行模式的处理器生成访问事务。 访问事务使用包含与页面和访问信息相关的配置设置的配置存储进行配置。 访问检查电路，其耦合到配置设置和访问信息，并且如果访问事务有效则生成访问许可信号。

公开(公告)号：DE112011103196T5

公开(公告)日：2013-09-19

申请号：DE112011103196

申请日：2011-09-23

Applicant: INTEL CORP

Inventor： WIEDEMEIER JEFF ,  GOLLIVER ROGER ,  SAMUDRALA SRIDHAR

IPC: G06F15/76 ,  G06F7/00 ,  G06F9/30

Abstract: Beschrieben wird eine Vektor-Funktionseinheit, die auf einem Halbleiterchip implementiert ist, zum Ausführen von Vektoroperationen mit der Dimension N. Die Vektor-Funktionseinheit hat N Funktionseinheiten. Jede der N Funktionseinheiten hat eine Logikschaltung, um Folgendes auszuführen: Eine erste Ganzzahlen-Multiply-Add-Anweisung, die höchstwertige Bits, jedoch nicht niedrigstwertige Bits, einer ersten Ganzzahlen-Multiply-Add-Berechnung bereitstellt, und eine zweite Ganzzahlen-Multiply-Add-Anweisung, die niedrigstwertige Bits, jedoch nicht höchstwertige Bits, einer zweiten Ganzzahlen-Multiply-Add-Berechnung bereitstellt.

公开(公告)号：DE112011103211T5

公开(公告)日：2013-07-04

申请号：DE112011103211

申请日：2011-09-24

Applicant: INTEL CORP

Inventor： GOLLIVER ROGER ,  WIEDEMEIER JEFF ,  SAMUDRALA SRIDHAR

IPC: G06F9/305 ,  G06F1/00 ,  G06F9/30 ,  G06F9/44

Abstract: Ein Halbleiterprozessor wird beschrieben. Der Halbleiterprozessor umfasst einen Logikschaltkreis zum Ausführen einer Instruktion zur logischen Reduktion. Der Logikschaltkreis umfasst einen Swizzle-Schaltkreis zum Swizzlen von Elementen eines Vektors zum Bilden eines Swizzle-Vektors. Der Logikschaltkreis umfasst auch einen Vektorlogikschaltkreis zum Durchführen einer vektorlogischen Operation auf dem Vektor und dem Swizzle-Vektor.

公开(公告)号：DE10196440T5

公开(公告)日：2004-04-29

申请号：DE10196440

申请日：2001-07-13

Applicant: INTEL CORP

Inventor： GOLLIVER ROGER ,  SUTTON II JAMES ,  LIN DERRICK ,  THAKKAR SHREEKANT ,  NEIGER GILBERT ,  MCKEEN FRANCIS ,  HERBERT HOWARD ,  RENERIS KENNETH ,  ELLISON CARL

IPC: G06F12/14 ,  G06F1/00

公开(公告)号：EP2798499A4

公开(公告)日：2015-10-21

申请号：EP11878669

申请日：2011-12-27

Applicant: INTEL CORP

Inventor： GREENFIELD MICHAEL R ,  GOLLIVER ROGER

IPC: G06F12/00 ,  G06F9/50 ,  G06F12/02 ,  G06F13/18

CPC classification number: G06F3/0608 ,  G06F3/0604 ,  G06F3/0611 ,  G06F3/0631 ,  G06F3/0638 ,  G06F3/0647 ,  G06F3/0653 ,  G06F3/067 ,  G06F3/0683 ,  G06F9/5016 ,  G06F12/02 ,  G06F12/023 ,  G06F13/18 ,  G06F2209/501 ,  G06F2209/5021 ,  G06F2212/1044

Abstract: Methods, articles of manufacture, and apparatus are disclosed to manage workload memory allocation. An example method includes identifying a primary memory and a secondary memory associated with a platform, the secondary memory having first performance metrics different from second performance metrics of the primary memory, identifying access metrics associated with a plurality of data elements invoked by a workload during execution on the platform, prioritizing a list of the plurality of data elements based on the access metrics associated with corresponding ones of the plurality of data elements, and reallocating a first one of the plurality of data elements from the primary memory to the secondary memory based on the priority of the first one of the plurality of memory elements.