公开(公告)号：WO1997048052A1

公开(公告)日：1997-12-18

申请号：PCT/US1997009059

申请日：1997-05-27

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  SOLOMON, Gary ,  RABE, Jeff ,  ABRAMSON, Darren

IPC: G06F13/00

CPC classification number: G06F13/4018 ,  G06F13/4036

Abstract: A collection buffering scheme for a computer system having agents (100) of a pre-emptible bus (4) and a non-pre-emptible bus (6). An agent (110) of the non-pre-emptible bus (6), having a data width capability of N bits, when receiving a grant to write to the pre-emptible bus (4), writes instead to a collection buffer (80) capable of holding a block of more than one N bit data segments. When the collection buffer (80) is filled, the collection buffer (80) writes the entire block of data segments over the pre-emptible bus (4) to a CPU (10) or memory (60) of the computer system. Preferably, the collection buffer (80) is filled when the block size is equal to the data width capability of the pre-emptible bus (4), such that a single write to the pre-emptible bus (4) utilizes the entire capacity of the pre-emptible bus (4) in a given data transaction. Further, where the system has a CPU posting buffer (55), a system lock-up prevention negotiator is provided that drains and disables the CPU posting buffer (55) during the data transaction.

Abstract translation: 一种用于具有可预占总线（4）和不可预先排除总线（6）的代理（100）的计算机系统的收集缓冲方案。 当接收到写入可预占总线（4）的授权时，具有N位的数据宽度能力的不可预先总线（6）的代理（110）代替写入收集缓冲器（80） ）能够保存多于一个N位数据段的块。 当收集缓冲器（80）被填充时，收集缓冲器（80）将整个数据段块写入可预留的总线（4）上，以写入计算机系统的CPU（10）或存储器（60）。 优选地，当块大小等于可预充电总线（4）的数据宽度能力时，收集缓冲器（80）被填充，使得对可预留总线（4）的单个写入利用了 在一个给定的数据交易中的可预见的总线（4）。 此外，在系统具有CPU发布缓冲器（55）的情况下，提供在数据交易期间排出并禁用CPU发布缓冲器（55）的系统锁定防止协商者。

公开(公告)号：WO2007117901A1

公开(公告)日：2007-10-18

申请号：PCT/US2007/064478

申请日：2007-03-21

Applicant: INTEL CORPORATION ,  DERR, Michael ,  ABRAMSON, Darren ,  DOUCETTE, Bryan ,  VADIVELU, Karthi

Inventor： DERR, Michael ,  ABRAMSON, Darren ,  DOUCETTE, Bryan ,  VADIVELU, Karthi

IPC: G06F1/00 ,  G06F1/26 ,  G06F13/00

CPC classification number: G06F1/3203 ,  G06F1/3253 ,  Y02D10/151 ,  Y02D50/20

Abstract: A method, apparatus, and system to synchronize multiple host controllers with non-uniform frame rates. The apparatus includes a first host controller, a second host controller, and logic. The first host controller is configured to access memory at a first frame rate. The second host controller is configured to access the memory at a second frame rate which is different from the first frame rate. The logic is coupled to the first and second host controllers to synchronize the memory accesses of the first and second host controllers at a common frame rate. Other embodiments are described.

Abstract translation: 一种以非均匀帧速率同步多个主机控制器的方法，装置和系统。 该装置包括第一主机控制器，第二主机控制器和逻辑。 第一主机控制器被配置为以第一帧速率访问存储器。 第二主机控制器被配置为以与第一帧速率不同的第二帧速率访问存储器。 该逻辑耦合到第一和第二主机控制器以以公共帧速率同步第一和第二主机控制器的存储器访问。 描述其他实施例。

公开(公告)号：WO2016195904A1

公开(公告)日：2016-12-08

申请号：PCT/US2016/030951

申请日：2016-05-05

Applicant: INTEL CORPORATION

Inventor： KLINGLESMITH, Michael, T. ,  KANG, Chang, Yong ,  DE GRUIJL, Robert ,  SCHOINAS, Ioannis, T. ,  ABRAMSON, Darren ,  LEE, Khee, Wooi

IPC: G06F13/40 ,  G06F13/42 ,  G06F15/78 ,  G06F13/12

CPC classification number: G06F13/4282 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/068 ,  G06F12/0828 ,  G06F13/1663 ,  G06F2212/621

Abstract: In one embodiment, a system includes: a first root space associated with a first root space identifier and including at least one first host processor and a first agent, the at least one first host processor and the first agent associated with the first root space identifier; a second root space associated with a second root space identifier and including at least one second host processor and a second agent, the at least one second host processor and the second agent associated with the second root space identifier; and a shared fabric to couple the first root space and the second root space, the shared fabric to route a transaction to the first root space or the second root space based at least in part on a root space field of the transaction. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，系统包括：与第一根空间标识符相关联并包括至少一个第一主处理器和第一代理的第一根空间，所述至少一个第一主处理器和与第一根空间标识符相关联的第一代理 ; 与第二根空间标识符相关联并包括至少一个第二主处理器和第二代理的第二根空间，所述至少一个第二主处理器和与所述第二根空间标识符相关联的第二代理; 以及共享结构，用于耦合所述第一根空间和所述第二根空间，所述共享结构至少部分地基于所述事务的根空间字段来将事务路由到所述第一根空间或所述第二根空间。 描述和要求保护其他实施例。

公开(公告)号：EP3304328A1

公开(公告)日：2018-04-11

申请号：EP16803938.6

申请日：2016-05-05

Applicant: INTEL Corporation

Inventor： KLINGLESMITH, Michael, T. ,  KANG, Chang, Yong ,  DE GRUIJL, Robert ,  SCHOINAS, Ioannis, T. ,  ABRAMSON, Darren ,  LEE, Khee, Wooi

IPC: G06F13/40 ,  G06F13/42 ,  G06F15/78 ,  G06F13/12

CPC classification number: G06F13/4282 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/068 ,  G06F12/0828 ,  G06F13/1663 ,  G06F2212/621

Abstract: In one embodiment, a system includes: a first root space associated with a first root space identifier and including at least one first host processor and a first agent, the at least one first host processor and the first agent associated with the first root space identifier; a second root space associated with a second root space identifier and including at least one second host processor and a second agent, the at least one second host processor and the second agent associated with the second root space identifier; and a shared fabric to couple the first root space and the second root space, the shared fabric to route a transaction to the first root space or the second root space based at least in part on a root space field of the transaction. Other embodiments are described and claimed.