公开(公告)号：WO1997048052A1

公开(公告)日：1997-12-18

申请号：PCT/US1997009059

申请日：1997-05-27

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  SOLOMON, Gary ,  RABE, Jeff ,  ABRAMSON, Darren

IPC: G06F13/00

CPC classification number: G06F13/4018 ,  G06F13/4036

Abstract: A collection buffering scheme for a computer system having agents (100) of a pre-emptible bus (4) and a non-pre-emptible bus (6). An agent (110) of the non-pre-emptible bus (6), having a data width capability of N bits, when receiving a grant to write to the pre-emptible bus (4), writes instead to a collection buffer (80) capable of holding a block of more than one N bit data segments. When the collection buffer (80) is filled, the collection buffer (80) writes the entire block of data segments over the pre-emptible bus (4) to a CPU (10) or memory (60) of the computer system. Preferably, the collection buffer (80) is filled when the block size is equal to the data width capability of the pre-emptible bus (4), such that a single write to the pre-emptible bus (4) utilizes the entire capacity of the pre-emptible bus (4) in a given data transaction. Further, where the system has a CPU posting buffer (55), a system lock-up prevention negotiator is provided that drains and disables the CPU posting buffer (55) during the data transaction.

Abstract translation: 一种用于具有可预占总线（4）和不可预先排除总线（6）的代理（100）的计算机系统的收集缓冲方案。 当接收到写入可预占总线（4）的授权时，具有N位的数据宽度能力的不可预先总线（6）的代理（110）代替写入收集缓冲器（80） ）能够保存多于一个N位数据段的块。 当收集缓冲器（80）被填充时，收集缓冲器（80）将整个数据段块写入可预留的总线（4）上，以写入计算机系统的CPU（10）或存储器（60）。 优选地，当块大小等于可预充电总线（4）的数据宽度能力时，收集缓冲器（80）被填充，使得对可预留总线（4）的单个写入利用了 在一个给定的数据交易中的可预见的总线（4）。 此外，在系统具有CPU发布缓冲器（55）的情况下，提供在数据交易期间排出并禁用CPU发布缓冲器（55）的系统锁定防止协商者。

公开(公告)号：WO2005015858A1

公开(公告)日：2005-02-17

申请号：PCT/US2004/025217

申请日：2004-08-04

Applicant: INTEL CORPORATION (a Corporation of Delaware) ,  SOLOMON, Gary ,  CHRIST, Chris ,  FEUERSTRAETER, Mark ,  HAN, Woojong

Inventor： SOLOMON, Gary ,  CHRIST, Chris ,  FEUERSTRAETER, Mark ,  HAN, Woojong

IPC: H04L12/56

CPC classification number: H04L47/10 ,  H04L41/12 ,  H04L47/15 ,  H04L47/16 ,  H04L47/2433 ,  H04L47/2441 ,  H04L47/30

Abstract: A method and apparatus for assigning data traffic classes to virtual channels in communications networks in generally described. In accordance with one embodiment of the invention, a node receiving a data packet including content to initialize a virtual channel on a point-to-point communication link to another node, initializing the virtual channel, based on the content, and mapping a data traffic class to the initialized virtual channel.

Abstract translation: 一种用于将数据业务等级分配给通信网络中的虚拟信道的方法和装置。 根据本发明的一个实施例，一种接收包括内容的数据分组的节点，以便在到另一节点的点对点通信链路上初始化虚拟频道，基于内容初始化虚拟频道，并映射数据业务 类到初始化的虚拟通道。

公开(公告)号：WO2005015830A1

公开(公告)日：2005-02-17

申请号：PCT/US2004/025213

申请日：2004-08-04

Applicant: INTEL CORPORATION ,  SOLOMON, Gary ,  CHRIST, Chris ,  FEUERSTRAETER, Mark ,  HAN, Woojong

Inventor： SOLOMON, Gary ,  CHRIST, Chris ,  FEUERSTRAETER, Mark ,  HAN, Woojong

IPC: H04L12/24

CPC classification number: H04L47/10 ,  H04L41/12 ,  H04L47/15 ,  H04L47/16 ,  H04L47/2433 ,  H04L47/2441 ,  H04L47/30

Abstract: A method and apparatus for signaling virtual channel support in communication networks. A node receives a data packet from another node to examine whether the other node commonly supports one or more virtual channels of a given type on a point-to-point communication link (101) between the nodes, and the node signaling common support for one or more virtual channels of a given type, based on the content in the received data packet that indicates whether the other node transmitting the data packet has adequate queue resources to support one or more virtual channels of a given type, and based on whether the node has adequate queue resources to support the one or more virtual channels of a given type.

Abstract translation: 一种用于在通信网络中信令虚拟信道支持的方法和装置。 节点从另一节点接收数据分组以检查另一节点是否通常在节点之间的点对点通信链路（101）上支持给定类型的一个或多个虚拟信道，并且节点信令共同支持一个 基于接收到的数据分组中的内容，指示发送数据分组的其他节点是否具有足够的队列资源以支持给定类型的一个或多个虚拟信道，并且基于节点 具有足够的队列资源来支持给定类型的一个或多个虚拟通道。

公开(公告)号：WO1993000749A1

公开(公告)日：1993-01-07

申请号：PCT/US1992005346

申请日：1992-06-24

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  SOLOMON, Gary

IPC: H04B01/00

CPC classification number: G06F3/14

Abstract: A standard interface between a system motherboard (12) and a control card (10) that can operate different types of screens, including LCD and VGA monitors. The interface has a plurality of pins (P1-P10) each designated to a particular signal or power line. The signals and power provided by the interface allow the design of a control card (10) that can drive any type of monitor of LCD screen.

Abstract translation: 系统主板（12）和控制卡（10）之间的标准接口，可以操作不同类型的屏幕，包括LCD和VGA显示器。 接口具有多个针对特定信号或电力线指定的引脚（P1-P10）。 接口提供的信号和电源允许设计可以驱动LCD屏幕的任何类型的显示器的控制卡（10）。

公开(公告)号：WO2010002660A3

公开(公告)日：2010-01-07

申请号：PCT/US2009/048449

申请日：2009-06-24

Applicant: INTEL CORPORATION ,  SOLOMON, Gary ,  SCHAEFER, Joe ,  DUNSTAN, Robert, A. ,  SAUNDERS, Brad

Inventor： SOLOMON, Gary ,  SCHAEFER, Joe ,  DUNSTAN, Robert, A. ,  SAUNDERS, Brad

IPC: G06F13/00 ,  G06F1/00

Abstract: In some embodiments a Universal Serial Bus cable includes a first differential pair to transmit bus signals, and a second differential pair to transmit bus signals in a same direction as the bus signals transmitted by the first differential pair. In this manner, a bandwidth of the Universal Serial Bus cable is doubled in that same direction. Other embodiments are described and claimed.

公开(公告)号：WO2003058460A2

公开(公告)日：2003-07-17

申请号：PCT/US2002/039156

申请日：2002-12-06

Applicant: INTEL CORPORATION

Inventor： HARRIMAN, David ,  LEE, David ,  CRETA, Kenneth ,  AJANOVIC, Jasmin ,  SOLOMON, Gary

IPC: G06F13/00

CPC classification number: G06F13/4282 ,  G06F2213/0026

Abstract: A requesting device and a completer device are coupled via a high-speed serial interface within a computer system. The requesting device transmits a packet for a request transaction to a completer device. The completer device checks for error conditions in the course of servicing the request. If an error condition is found, the completer device transmits a completion packet with a completion status of something other than successful. The completion packet includes a completer identification field. The requesting device records the completer identification value and indicates in a register that a completion packet has been received with a non-successful completion status.

Abstract translation: 请求设备和完成者设备通过计算机系统内的高速串行接口耦合。 请求设备将请求交易的分组发送给完成者设备。 完成程序设备在服务请求过程中检查错误情况。 如果发现错误条件，则完成器设备发送具有除成功以外的完成状态的完成包。 完成数据包包括完成者标识字段。 请求设备记录完成者标识值并在一个寄存器中指示已经收到一个完成数据包，但未成功完成状态。

公开(公告)号：WO2003040872A3

公开(公告)日：2003-05-15

申请号：PCT/US2002/034488

申请日：2002-10-30

Applicant: INTEL CORPORATION

Inventor： AWSIENKO, Oleg ,  BUTLER, Edward ,  MCALPINE, Gary ,  MINTURN, Dave ,  SCHAEFER, Joseph ,  SOLOMON, Gary

IPC: G06F9/00

Abstract: A multi-domain processing system includes a multi-dimensional switching fabric to provide intra-domain and inter-domain communication within the system.

公开(公告)号：WO2005026970A2

公开(公告)日：2005-03-24

申请号：PCT/US2004/028731

申请日：2004-09-03

Applicant: INTEL CORPORATION (a Delaware Corporation)

Inventor： ISKIYAN, Peter ,  SCHAEFER, Joseph ,  SOLOMON, Gary

IPC: G06F13/00

CPC classification number: G06F9/4411

Abstract: A method and an apparatus to configure a multi-port device are disclosed. The method includes defining a first set of pointers, one for each port of the multi-port device, and storing the first set of pointers in one or more capability structures of the multi-port device.

Abstract translation: 公开了一种配置多端口设备的方法和装置。 该方法包括定义第一组指针，一个针对多端口设备的每个端口，以及将第一组指针存储在多端口设备的一个或多个能力结构中。

公开(公告)号：WO2004095246A1

公开(公告)日：2004-11-04

申请号：PCT/US2004/003351

申请日：2004-02-17

Applicant: INTEL CORPORATION

Inventor： NAVEH, Alon ,  KUMAR, Mohan ,  GUTMAN, Mickey ,  MARTWICK, Andrew ,  SOLOMON, Gary

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/3209 ,  H04L12/40039 ,  Y02D10/171

Abstract: Briefly, system and method for message-based power management which may be used, for example, in computer systems and communications networks. Embodiments of the present invention may include, for example, a device connected to a power management controller (PMC); the device and/or the PMC may send, receive, and/or process power management event (PME) messages. Embodiments of the present invention may operate using links in communicative and/or non-communicative modes. Embodiments of the present invention may include a switch, to send/ receive, process, create, re-format and/or route one or more PME message on behalf of various devices, for example, a Peripheral Component Interconnect (PCI) device.

Abstract translation: 简而言之，用于例如计算机系统和通信网络中的基于消息的电力管理的系统和方法。 本发明的实施例可以包括例如连接到电力管理控制器（PMC）的设备; 设备和/或PMC可以发送，接收和/或处理电源管理事件（PME）消息。 本发明的实施例可以使用通信和/或非通信模式中的链路来操作。 本发明的实施例可以包括代表诸如外围组件互连（PCI）设备的各种设备发送/接收，处理，创建，重新格式化和/或路由一个或多个PME消息的交换机。

公开(公告)号：WO2004019562A2

公开(公告)日：2004-03-04

申请号：PCT/US2003/026245

申请日：2003-08-22

Applicant: INTEL CORPORATION (A DELAWARE CORPORATION)

Inventor： SOLOMON, Gary ,  HARRIMAN, David

IPC: H04L12/54

CPC classification number: H04L49/252 ,  H04L49/3009 ,  H04L49/555

Abstract: Disclosed are a system and method for forwarding data packets from ingress ports to egress ports on a switch. A forwarding circuit may commence forwarding data packets from an ingress port through a switch fabric to a transmit queue of an egress port prior to completion of a checksum operation.

Abstract translation: 公开了用于将来自入口端口的数据分组转发到交换机上的出口端口的系统和方法。 在完成校验和操作之前，转发电路可以开始将来自入口端口的数据分组通过交换结构转发到出口端口的传输队列。