公开(公告)号：WO2023048804A1

公开(公告)日：2023-03-30

申请号：PCT/US2022/037742

申请日：2022-07-20

Applicant: INTEL CORPORATION

Inventor： ECTON, Jeremy, D. ,  PIETAMBARAM, Srinivas, V. ,  MARIN, Brandon, C. ,  CHEN, Haobo ,  ARANA, Leonel

IPC: H01L23/498 ,  H01L23/15 ,  H01L23/00 ,  H01L21/48 ,  H01L23/14

Abstract: Embodiments include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a first substrate, and a second substrate coupled to the first substrate. In an embodiment, the second substrate comprises a core, and the core comprises an organic material. In an embodiment, a third substrate is coupled to the second substrate, and the third substrate comprises a glass layer.

公开(公告)号：WO2022203788A1

公开(公告)日：2022-09-29

申请号：PCT/US2022/017022

申请日：2022-02-18

Applicant: INTEL CORPORATION

Inventor： CHEN, Haobo ,  GUO, Xiaoying ,  FENG, Hongxia ,  DARMAWIKARTA, Kristof ,  NIE, Bai ,  IBRAHIM, Tarek A. ,  DUAN, Gang ,  ECTON, Jeremy D. ,  LI, Sheng C. ,  ARANA, Leonel

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

Abstract: Embodiments disclosed herein include a multi-die packages with an embedded bridge and a thinned surface. In an example, a multi-die interconnect structure includes a package substrate having a cavity. A bridge die is in the cavity of the package substrate, the bridge die including silicon. A dielectric material is over the package substrate, over the bridge die, and in the cavity. A plurality of conductive bond pads is on the dielectric material. The multi-die interconnect structure further includes a plurality of conductive pillars, individual ones of the plurality of conductive pillars on a corresponding one of the plurality of conductive bond pads. A solder resist material is on the dielectric material, on exposed portions of the plurality of conductive bond pads, and laterally surrounding the plurality of conductive pillars. The plurality of conductive pillars has a top surface above a top surface of the solder resist material.

公开(公告)号：EP4406017A1

公开(公告)日：2024-07-31

申请号：EP22873354.9

申请日：2022-07-20

Applicant: Intel Corporation

Inventor： ECTON, Jeremy, D. ,  PIETAMBARAM, Srinivas, V. ,  MARIN, Brandon, C. ,  CHEN, Haobo ,  ARANA, Leonel

IPC: H01L23/498 ,  H01L23/15 ,  H01L23/00 ,  H01L21/48 ,  H01L23/14

CPC classification number: H01L23/5385 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/15 ,  H01L25/0655 ,  H01L24/16 ,  H01L24/17

公开(公告)号：EP4184569A3

公开(公告)日：2023-08-09

申请号：EP22201685.9

申请日：2022-10-14

Applicant: INTEL Corporation

Inventor： SHAN, Bohan ,  CHEN, Haobo ,  KARHADE, Omkar ,  SANKARASUBRAMANIAN, Malavarayan ,  XU, Dingying ,  DUAN, Gang ,  NIE, Bai ,  GUO, Xiaoying ,  DARMAWIKARTA, Kristof ,  FENG, Hongxia ,  PIETAMBARAM, Srinivas V. ,  ECTON, Jeremy

IPC: H01L23/485 ,  H01L21/603 ,  H01L25/065 ,  H05K3/34

Abstract: In a microelectronic package, one or more solder joints (130A-B, 206A-D, 226, 640) between two substrates (102, 104, 202A, 202B, 204, 224, 228, 600, 630) are formed as full IMC (intermetallic compound) solder joints, while other solder joints (132, 210, 220, 642) may be formed as regular solder joints. The full IMC solder joint (130A-B, 206A-D, 226, 640) includes a continuous layer (e.g., from a top pad (124, 128, 636) to a bottom pad (122, 126, 606)) of intermetallic compounds and may include copper particles (302) throughout the full IMC solder joints (130A-B, 206A-D, 226, 640). The full IMC solder joint (130A-B, 206A-D, 226, 640) may include cured epoxy from a no-remelt solder around the continuous layer of IMCs. The full IMC solder joint (130A-B, 206A-D, 226, 640) has a melting point that is higher than that of the regular solder joints (132, 210, 220, 642). The full IMC solder joint (130A-B, 206A-D, 226, 640) may be between dummy pads (126, 128, 606, 636) on the first and second substrates (102, 104, 600, 630) or may include an interconnect for power delivery between the first substrate (102, 600) and the second substrate (104, 630) or an input/output (I/O) interconnect between the first substrate (102, 600) and the second substrate (104, 630). The first substrate (102, 204, 224, 600) and the second substrate (104, 202A, 202B, 228, 630) may include one or more of: a substrate, a die, a bridge die, an interposer, a patch, a thin film, a motherboard, a redistribution layer (RDL), and an organic PCB, in particular, the first substrate (204) may be a core substrate and the second substrate (202A, 202B) may be a substrate patch, or the full IMC solder joint (226) may be located in a via (222) in the first substrate (224), wherein the second substrate may be a bridge die (228). The solder joints (130A-B, 206A-D, 226, 640) may include at least three full IMC solder joints, wherein the number of full IMC solder joints is in a range of one solder joint to 50% of all solder joints. In a method of manufacturing the microelectronic package, regular solder (602) is dispensed on a plurality of conductive contacts (604) of a first substrate (600), no-remelt solder (620) is dispensed on another conductive contact (606) of the first substrate (600), and a second substrate (630) is bonded to the first substrate (600), forming the full IMC solder joint (640) from the no-remelt solder (620). The no-remelt solder (620) may be a TLPS (transient liquid phase sintering) paste, e.g., a solder paste that includes copper (Cu) particles together with tin (Sn) or tin alloy (such as Sn-Bi) particles dispersed in a flux system, such as an epoxy flux. The no-remelt solder (620) may have a higher melting point than the regular solder (602). The location of the full IMC solder joints (130A-B, 206A-D, 226, 640) may be selected to maximize mechanical stability both during downstream reflow (eliminating die or substrate movement, during multiple thermal processing steps (e.g., reflow steps) while forming hierarchical interconnections) and of the final package. For example, the full IMC joints (130A-B, 206A-D, 226, 640) may be formed in areas other than corners to prevent cracking. The full IMC (130A-B, 206A-D, 226, 640) joints may also be distributed (e.g., distributed uniformly) amongst the regular solder joints to increase stability during assembly in all areas between the substrates.

公开(公告)号：EP4184569A2

公开(公告)日：2023-05-24

申请号：EP22201685.9

申请日：2022-10-14

Applicant: INTEL Corporation

Inventor： SHAN, Bohan ,  CHEN, Haobo ,  KARHADE, Omkar ,  SANKARASUBRAMANIAN, Malavarayan ,  XU, Dingying ,  DUAN, Gang ,  NIE, Bai ,  GUO, Xiaoying ,  DARMAWIKARTA, Kristof ,  FENG, Hongxia ,  PIETAMBARAM, Srinivas V. ,  ECTON, Jeremy

IPC: H01L23/485 ,  H01L21/603 ,  H01L25/065 ,  H05K3/34

Abstract: In a microelectronic package, one or more solder joints (130A-B, 206A-D, 226, 640) between two substrates (102, 104, 202A, 202B, 204, 224, 228, 600, 630) are formed as full IMC (intermetallic compound) solder joints, while other solder joints (132, 210, 220, 642) may be formed as regular solder joints. The full IMC solder joint (130A-B, 206A-D, 226, 640) includes a continuous layer (e.g., from a top pad (124, 128, 636) to a bottom pad (122, 126, 606)) of intermetallic compounds and may include copper particles (302) throughout the full IMC solder joints (130A-B, 206A-D, 226, 640). The full IMC solder joint (130A-B, 206A-D, 226, 640) may include cured epoxy from a no-remelt solder around the continuous layer of IMCs. The full IMC solder joint (130A-B, 206A-D, 226, 640) has a melting point that is higher than that of the regular solder joints (132, 210, 220, 642). The full IMC solder joint (130A-B, 206A-D, 226, 640) may be between dummy pads (126, 128, 606, 636) on the first and second substrates (102, 104, 600, 630) or may include an interconnect for power delivery between the first substrate (102, 600) and the second substrate (104, 630) or an input/output (I/O) interconnect between the first substrate (102, 600) and the second substrate (104, 630). The first substrate (102, 204, 224, 600) and the second substrate (104, 202A, 202B, 228, 630) may include one or more of: a substrate, a die, a bridge die, an interposer, a patch, a thin film, a motherboard, a redistribution layer (RDL), and an organic PCB, in particular, the first substrate (204) may be a core substrate and the second substrate (202A, 202B) may be a substrate patch, or the full IMC solder joint (226) may be located in a via (222) in the first substrate (224), wherein the second substrate may be a bridge die (228). The solder joints (130A-B, 206A-D, 226, 640) may include at least three full IMC solder joints, wherein the number of full IMC solder joints is in a range of one solder joint to 50% of all solder joints. In a method of manufacturing the microelectronic package, regular solder (602) is dispensed on a plurality of conductive contacts (604) of a first substrate (600), no-remelt solder (620) is dispensed on another conductive contact (606) of the first substrate (600), and a second substrate (630) is bonded to the first substrate (600), forming the full IMC solder joint (640) from the no-remelt solder (620). The no-remelt solder (620) may be a TLPS (transient liquid phase sintering) paste, e.g., a solder paste that includes copper (Cu) particles together with tin (Sn) or tin alloy (such as Sn-Bi) particles dispersed in a flux system, such as an epoxy flux. The no-remelt solder (620) may have a higher melting point than the regular solder (602). The location of the full IMC solder joints (130A-B, 206A-D, 226, 640) may be selected to maximize mechanical stability both during downstream reflow (eliminating die or substrate movement, during multiple thermal processing steps (e.g., reflow steps) while forming hierarchical interconnections) and of the final package. For example, the full IMC joints (130A-B, 206A-D, 226, 640) may be formed in areas other than corners to prevent cracking. The full IMC (130A-B, 206A-D, 226, 640) joints may also be distributed (e.g., distributed uniformly) amongst the regular solder joints to increase stability during assembly in all areas between the substrates.

公开(公告)号：EP4531091A1

公开(公告)日：2025-04-02

申请号：EP24186090.7

申请日：2024-07-02

Applicant: INTEL Corporation

Inventor： DANI, Ashay ,  BAI, Yiqun ,  GOKHALE, Shripad ,  LI, Yonggang Yong ,  XU, Dingying ,  SENEVIRATNE, Dilan ,  CETEGEN, Edvin ,  GUPTA, Mohit ,  MARIN, Brandon C. ,  SRINIVASAN, Kartik ,  RAMANUJA PIETAMBARAM, Srinivas Venkata ,  FENG, Hongxia ,  DUAN, Gang ,  HAN, Jung Kyu ,  STACEY, Joshua ,  HEATON, Thomas ,  GAMBA, Jason ,  GUO, Xiaoying ,  HAEHN, Nicholas ,  JONES, Jesse ,  KONG, Jieying ,  ECTON, Jeremy ,  JIMENEZ, Andrew ,  TANAKA, Hiroki ,  MCREE, Robin ,  BRYKS, Whitney ,  LIN, Ziyin ,  NIE, Bai ,  CHEN, Haobo ,  MO, Jianyong ,  ARRINGTON, Kyle ,  VEHONSKY, Jacob ,  WATSON, MAKOYI ,  GARELICK, Aaron ,  SHAN, Bohan ,  KAYA, Mine ,  WAIMIN, Jose ,  XIE, Zhixin ,  LI, Yi ,  MOHAMMADIGHALENI, Mahdi ,  LI, Yuqin ,  LAI, Shuqi ,  CHEN, Shaojiang ,  SONG, Hanyu ,  MU, Bin ,  TRIPATHI, Astitva ,  CARRAZZONE, Ryan ,  WANG, Yekan ,  SREERAMAGIRI, Praveen ,  EL KHATIB, Ibrahim ,  AJAMI, Hassan ,  PAGE, Mitchell

IPC: H01L23/15 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/13

Abstract: Embodiments disclosed herein include apparatuses with glass core package substrates. In an embodiment, an apparatus comprises a substrate with a first surface and a second surface opposite from the first surface. A sidewall is between the first surface and the second surface, and the substrate comprises a glass layer. In an embodiment, a via is provided through the substrate between the first surface and the second surface, and the via is electrically conductive. In an embodiment, a layer in contact with the sidewall of the substrate surrounds a perimeter of the substrate.

公开(公告)号：EP4546420A1

公开(公告)日：2025-04-30

申请号：EP24196789.2

申请日：2024-08-27

Applicant: INTEL Corporation

Inventor： DUAN, Gang ,  KANAOKA, Yosuke ,  LIU, Minglu ,  PIETAMBARAM, Srinivas V. ,  MARIN, Brandon C. ,  SHAN, Bohan ,  CHEN, Haobo ,  ECTON, Jeremy ,  DUONG, Benjamin T. ,  NAD, Suddhasattwa

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer having first dies in a first insulating material; a second layer on the first layer, the second layer including second dies having a first thickness and third dies having a second thickness different than the first thickness, the second dies and the third dies in a second insulating material, wherein the second dies and third dies have a first surface and an opposing second surface, and wherein the first surfaces of the second and third dies have a combined surface area between 3,000 square millimeters (mm 2 ) and 9,000 mm 2 ; and a redistribution layer (RDL) between the first layer and the second layer, the RDL including conductive pathways, wherein the first dies are electrically coupled to the second dies and the third dies by the conductive pathways and by interconnects.

公开(公告)号：EP4020039A1

公开(公告)日：2022-06-29

申请号：EP21197529.7

申请日：2021-09-17

Applicant: INTEL Corporation

Inventor： ALEKSOV, Aleksandar ,  MARIN, Brandon ,  PIETAMBARAM, Srinivas ,  ZHANG, Zhichao ,  DUAN, Gang ,  ECTON, Jeremy ,  TANAKA, Hiroki ,  VADLAMANI, Sai ,  NIE, Bai ,  CHEN, Haobo

IPC: G02B6/42

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such structures. In an embodiment, an electronic package comprises a package substrate, a first die over the package substrate, and a second die over the package substrate. In an embodiment, the electronic package further comprises an optical waveguide on the package substrate. In an embodiment, a first end of the optical waveguide is below the first die and a second end of the optical waveguide is below the second die. In an embodiment, the optical waveguide communicatively couples the first die to the second die.