公开(公告)号：WO2003058631A3

公开(公告)日：2003-07-17

申请号：PCT/US2002/040705

申请日：2002-12-18

Applicant: INTEL CORPORATION

Inventor： BLAKENSHIP, Robert ,  GEORGE, Robert ,  CRETA, Kenneth

IPC: G06F12/08

Abstract: Apparatus having a cache memory including cache lines configured to cache data sent from an input/output device and an eviction mechanism configured to evict data stored in one of the cache lines based on validity state information associated with the data stored in the one cache line. Each cache line has multiple portions, and validity bits are used to track the validity of respective portions of the cache line. The validity bits are set to predefined values responsive to the number of bytes written into the respective portions in one write transaction. The cache line is evicted by the eviction mechanism when the validity bits corresponding to the cache line all have the predefined values. The eviction mechanism is configured to evict the data even if the cache memory is not full.

公开(公告)号：WO2003058460A3

公开(公告)日：2003-07-17

申请号：PCT/US2002/039156

申请日：2002-12-06

Applicant: INTEL CORPORATION

Inventor： HARRIMAN, David ,  LEE, David ,  CRETA, Kenneth ,  AJANOVIC, Jasmin ,  SOLOMON, Gary

IPC: G06F13/40

Abstract: A requesting device and a completer device are coupled via a high-speed serial interface within a computer system. The requesting device transmits a packet for a request transaction to a completer device. The completer device checks for error conditions in the course of servicing the request. If an error condition is found, the completer device transmits a completion packet with a completion status of something other than successful. The completion packet includes a completer identification field. The requesting device records the completer identification value and indicates in a register that a completion packet has been received with a non-successful completion status.

公开(公告)号：WO2003019398A1

公开(公告)日：2003-03-06

申请号：PCT/US2002/024651

申请日：2002-08-01

Applicant: INTEL CORPORATION (a Delaware Corporation)

Inventor： CRETA, Kenneth ,  CONGDON, Bradford ,  RAMACHANDRAN, Deepak ,  RAND, Tony

IPC: G06F13/40

CPC classification number: G06F13/4013

Abstract: An input/output hub includes an inbound ordering queue (IOQ) to receive inbound transactions. All read and write transactions have a transaction completion. Peer-to-peer transactions are not permitted to reach a destination until after all prior writes in the IOQ have been completed. A write in a peer-to-peer transaction does not permit subsequent accesses to proceed until the write is guaranteed to be in an ordered domain of the destination. An IOQ read bypass buffer is provided to receive read transactions pushed from the IOQ to permit posted writes and read/write completions to progress through the IOQ. An outbound ordering queue (OOQ) stores outbound transactions and completions of the inbound transactions. The OOQ also issues write completions for posted writes. An OOQ read bypass buffer is provided to receive read transactions pushed from the OOQ to permit posted writes and read/write completions to progress through the OOQ. An unordered domain within the input/output hub receives the inbound transactions transmitted from an unordered protocol.

Abstract translation: 输入/输出集线器包括接收入站事务的入站订单队列（IOQ）。 所有读写事务都有一个事务完成。 在IOQ的所有事先写入完成之后，对等交易都不允许到达目的地。 在对等交易中的写入不允许后续访问继续进行，直到写保证在目的地的有序域中。 提供IOQ读取旁路缓冲区以接收从IOQ推送的读取事务，以允许发布的写入和读取/写入完成以通过IOQ进行。 出站订单队列（OOQ）存储入站事务的出站事务和完成。 OOQ还发布写入完成。 提供OOQ读取旁路缓冲区以接收从OOQ推送的读取事务，以允许发布的写入和读取/写入完成以通过OOQ进行。 输入/输出集线器内的无序域接收从无序协议发送的入站事务。

公开(公告)号：WO2003058460A2

公开(公告)日：2003-07-17

申请号：PCT/US2002/039156

申请日：2002-12-06

Applicant: INTEL CORPORATION

Inventor： HARRIMAN, David ,  LEE, David ,  CRETA, Kenneth ,  AJANOVIC, Jasmin ,  SOLOMON, Gary

IPC: G06F13/00

CPC classification number: G06F13/4282 ,  G06F2213/0026

Abstract: A requesting device and a completer device are coupled via a high-speed serial interface within a computer system. The requesting device transmits a packet for a request transaction to a completer device. The completer device checks for error conditions in the course of servicing the request. If an error condition is found, the completer device transmits a completion packet with a completion status of something other than successful. The completion packet includes a completer identification field. The requesting device records the completer identification value and indicates in a register that a completion packet has been received with a non-successful completion status.

Abstract translation: 请求设备和完成者设备通过计算机系统内的高速串行接口耦合。 请求设备将请求交易的分组发送给完成者设备。 完成程序设备在服务请求过程中检查错误情况。 如果发现错误条件，则完成器设备发送具有除成功以外的完成状态的完成包。 完成数据包包括完成者标识字段。 请求设备记录完成者标识值并在一个寄存器中指示已经收到一个完成数据包，但未成功完成状态。

公开(公告)号：WO2003019384A1

公开(公告)日：2003-03-06

申请号：PCT/US2002/024484

申请日：2002-08-02

Applicant: INTEL CORPORATION

Inventor： CRETA, Kenneth ,  BELL, Dennis ,  GEORGE, Robert

IPC: G06F12/08

CPC classification number: G06F12/0813 ,  G06F12/0817 ,  G06F12/0848

Abstract: A system and method utilizing distributed caches. More particularly, the present invention pertains to a scalable method of improving the bandwidth and latency performance of caches through the implementation of distributed caches. Distributed caches remove the detrimental architectural and implementation impacts of single monolithic cache systems.

Abstract translation: 一种利用分布式缓存的系统和方法。 更具体地，本发明涉及通过实施分布式高速缓存来改进高速缓存的带宽和延迟性能的可扩展方法。 分布式缓存消除了单块单块缓存系统的不利结构和实现影响。

公开(公告)号：WO2004095299A1

公开(公告)日：2004-11-04

申请号：PCT/US2004/004214

申请日：2004-02-11

Applicant: INTEL CORPORATION

Inventor： CRETA, Kenneth ,  MUTHRASANALLUR, Sridhar

IPC: G06F13/16

CPC classification number: G06F13/4027 ,  G06F2213/0026

Abstract: A method and an apparatus to combine and to send data dynamically are disclosed. The method comprises receiving data that partially satisfies a read request from a memory in response to a request, wherein the request is from a requester. The method further comprises forwarding the data to the requester if a port used to forward the data of the read request is idle. If the port is busy, the data is stored for combining with additional data that partially satisfies the read request as the additional data is received, and the combined data is forwarded to the requester when the port is not busy. In one embodiment, the port is a PCI Express TM port.

Abstract translation: 公开了一种动态地组合和发送数据的方法和装置。 所述方法包括响应于请求从所述存储器接收部分地满足读取请求的数据，其中所述请求来自请求者。 该方法还包括：如果用于转发读请求的数据的端口空闲，则将数据转发到请求者。 如果端口正忙，则当接收到附加数据时，数据被存储用于与部分满足读取请求的附加数据组合，并且当端口不忙时将组合的数据转发到请求者。 在一个实施例中，该端口是PCI Express TM端口。

公开(公告)号：WO2003058631A2

公开(公告)日：2003-07-17

申请号：PCT/US2002/040705

申请日：2002-12-18

Applicant: INTEL CORPORATION

Inventor： BLAKENSHIP, Robert ,  GEORGE, Robert ,  CRETA, Kenneth

IPC: G11C8/00

CPC classification number: G06F12/0804

Abstract: Apparatus having a cache memory including cache lines configured to cache data sent from an input/output device and an eviction mechanism configured to evict data stored in one of the cache lines based on validity state information associated with the data stored in the one cache line. Each cache line has multiple portions, and validity bits are used to track the validity of respective portions of the cache line. The validity bits are set to predefined values responsive to the number of bytes written into the respective portions in one write transaction. The cache line is evicted by the eviction mechanism when the validity bits corresponding to the cache line all have the predefined values. The eviction mechanism is configured to evict the data even if the cache memory is not full.

Abstract translation: 具有高速缓冲存储器的设备，所述高速缓冲存储器包括被配置为高速缓存从输入/输出设备发送的数据的高速缓存行，以及被配置为基于与所述高速缓存行中的 数据存储在一个缓存行中。 每个高速缓存行都有多个部分，有效位用于跟踪高速缓存行各个部分的有效性。 响应于在一次写入事务中写入相应部分的字节数，有效位被设置为预定值。 当对应于高速缓存行的有效位全部具有预定义值时，高速缓存行被驱逐机制驱逐。 即使高速缓存存储器未满，驱逐机制也会配置为驱逐数据。

公开(公告)号：WO2003019386A1

公开(公告)日：2003-03-06

申请号：PCT/US2002/025090

申请日：2002-08-06

Applicant: INTEL CORPORATION (a Delaware Corporation)

Inventor： CRETA, Kenneth ,  BELL, Dennis ,  BLANKENSHIP, Robert ,  CONGDON, Bradford ,  GEORGE, Robert ,  JANUARY, Duane

IPC: G06F12/08

CPC classification number: G06F12/0848 ,  G06F12/0802 ,  G06F12/0833 ,  G06F13/4059

Abstract: A caching input/output hub includes a host interface to connect with a host. At least one input/output interface is provided to connect with an input/output device. A write cache manages memory writes initiated by the input/output device. At least one read cache, separate from the write cache, provides a low-latency copy of data that is most likely to be used. The at least one read cache is in communication with the write cache. A cache directory is also provided to track cache lines in the write cache and the at least one read cache. The cache directory is in communication with the write cache and the at least one read cache.

Abstract translation: 缓存输入/输出集线器包括与主机连接的主机接口。 提供至少一个输入/输出接口以与输入/输出设备连接。 写缓存管理由输入/输出设备发起的存储器写入。 与写缓存分开的至少一个读缓存提供了最可能使用的低延迟数据副本。 至少一个读高速缓存与写高速缓存通信。 还提供缓存目录以跟踪写入高速缓存和至少一个读取高速缓存中的高速缓存行。 缓存目录与写缓存和至少一个读高速缓存通信。

公开(公告)号：EP1311956A2

公开(公告)日：2003-05-21

申请号：EP01959749.1

申请日：2001-08-14

Applicant: INTEL CORPORATION

Inventor： CRETA, Kenneth ,  LOOI, Lily ,  KUMAR, Akhilesh ,  KHARE, Manoj

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F12/0831 ,  G06F12/0835

Abstract: An approach for pipelining ordered input/output transactions to coherent memory in a distributed memory, cache coherent, multi-processor system. A prefetch engine prefetches data from the distributed, coherent memory in response to a transaction from an input/output bus directed to the distributed, coherent memory. An input/output coherent cache buffer receives the prefetched data and is kept coherent with the distributed, coherent memory and with other caching agents in the system.

公开(公告)号：EP1609072A1

公开(公告)日：2005-12-28

申请号：EP04710287.6

申请日：2004-02-11

Applicant: INTEL CORPORATION

Inventor： CRETA, Kenneth ,  MUTHRASANALLUR, Sridhar

IPC: G06F13/16 ,  G06F13/40

CPC classification number: G06F13/4027 ,  G06F2213/0026

Abstract: A method and an apparatus to combine and to send data dynamically are disclosed. The method comprises receiving data that partially satisfies a read request from a memory in response to a request, wherein the request is from a requester. The method further comprises forwarding the data to the requester if a port used to forward the data of the read request is idle. If the port is busy, the data is stored for combining with additional data that partially satisfies the read request as the additional data is received, and the combined data is forwarded to the requester when the port is not busy. In one embodiment, the port is a PCI ExpressTM port.