公开(公告)号：WO2006071944A2

公开(公告)日：2006-07-06

申请号：PCT/US2005/047276

申请日：2005-12-28

Applicant: INTEL CORPORATION ,  LEE, David ,  KULICK, Steve ,  RADHAKRISHNAN, Sivakumar

Inventor： LEE, David ,  KULICK, Steve ,  RADHAKRISHNAN, Sivakumar

IPC: G06F13/24 ,  G06F9/46

CPC classification number: G06F13/22 ,  G06F13/24

Abstract: In some embodiments, a method, apparatus and system to generate an interrupt by monitoring an external interface are presented. In this regard, an interrupt agent is introduced to communicate over a serial interface with an input/output (I/O) extender and to save a relevant status of the I/O extender in a memory. Other embodiments are also disclosed and claimed.

Abstract translation: 在一些实施例中，呈现通过监视外部接口来产生中断的方法，装置和系统。 在这方面，引入一个中断代理程序通过串行接口与输入/输出（I / O）扩展器进行通信，并将I / O扩展器的相关状态保存在存储器中。 还公开并要求保护其他实施例。

公开(公告)号：WO2003058460A3

公开(公告)日：2003-07-17

申请号：PCT/US2002/039156

申请日：2002-12-06

Applicant: INTEL CORPORATION

Inventor： HARRIMAN, David ,  LEE, David ,  CRETA, Kenneth ,  AJANOVIC, Jasmin ,  SOLOMON, Gary

IPC: G06F13/40

Abstract: A requesting device and a completer device are coupled via a high-speed serial interface within a computer system. The requesting device transmits a packet for a request transaction to a completer device. The completer device checks for error conditions in the course of servicing the request. If an error condition is found, the completer device transmits a completion packet with a completion status of something other than successful. The completion packet includes a completer identification field. The requesting device records the completer identification value and indicates in a register that a completion packet has been received with a non-successful completion status.

公开(公告)号：WO2004032417A1

公开(公告)日：2004-04-15

申请号：PCT/US2003/030056

申请日：2003-09-24

Applicant: INTEL CORPORATION

Inventor： LEE, David ,  GARY, Graunke, L. ,  TRAW, Brendan

IPC: H04L9/32

CPC classification number: H04L9/0844 ,  H04L2209/60

Abstract: In a cryptographic system, a nonce is removed from a communication stream. The nonce is encrypted based on a shared secret. The encrypted nonce is inserted into the communication stream. The encrypted nonce is removed from the communication stream. The encrypted nonce is decrypted based on the shared secret formed by an authenticated key exchange. The decrypted nonce is inserted into the communication stream. The nonce may be an A n value generated by a HDCP function. The authenticated key exchange may use Diffie-Hellman Key Exchange.

Abstract translation: 在密码系统中，从通信流中删除随机数。 该随机数是基于共享密钥进行加密的。 加密的随机数插入到通信流中。 加密的随机数从通信流中删除。 基于由认证密钥交换形成的共享秘密对加密的随机数进行解密。 解密的随机数被插入到通信流中。 随机数可以是由HDCP功能生成的值。 经认证的密钥交换可以使用Diffie-Hellman密钥交换。

公开(公告)号：WO2003058460A2

公开(公告)日：2003-07-17

申请号：PCT/US2002/039156

申请日：2002-12-06

Applicant: INTEL CORPORATION

Inventor： HARRIMAN, David ,  LEE, David ,  CRETA, Kenneth ,  AJANOVIC, Jasmin ,  SOLOMON, Gary

IPC: G06F13/00

CPC classification number: G06F13/4282 ,  G06F2213/0026

Abstract: A requesting device and a completer device are coupled via a high-speed serial interface within a computer system. The requesting device transmits a packet for a request transaction to a completer device. The completer device checks for error conditions in the course of servicing the request. If an error condition is found, the completer device transmits a completion packet with a completion status of something other than successful. The completion packet includes a completer identification field. The requesting device records the completer identification value and indicates in a register that a completion packet has been received with a non-successful completion status.

Abstract translation: 请求设备和完成者设备通过计算机系统内的高速串行接口耦合。 请求设备将请求交易的分组发送给完成者设备。 完成程序设备在服务请求过程中检查错误情况。 如果发现错误条件，则完成器设备发送具有除成功以外的完成状态的完成包。 完成数据包包括完成者标识字段。 请求设备记录完成者标识值并在一个寄存器中指示已经收到一个完成数据包，但未成功完成状态。

公开(公告)号：EP1141832B1

公开(公告)日：2008-10-22

申请号：EP99949955.1

申请日：1999-09-29

Applicant: Intel Corporation

Inventor： HOLLAND, Kenneth ,  LEE, David ,  MEREDITH, Susan

IPC: G06F11/16 ,  G06F13/42

CPC classification number: G06F13/4213 ,  G06F11/1679

Abstract: A computer system (50) includes a bus (52), a first bus device (60), a core circuit (58) and a second circuit (54). The first bus device (60) is coupled to the bus (52) and adapted to furnish a first indication of data to a portion of a bus (52) beginning at a first clock cycle. The bus is capable of skewing the first indication to produce a second indication of the data at another portion of the bus (52) beginning at another clock cycle. The second circuit (54) is coupled to the bus (52) and is adapted to receive an indication of a selected latency time. The second circuit (54) is also adapted to transfer the data to the core circuit (58) in response to the second indication and regulate the transfer so that the circuit receives the data beginning at the selected latency time after the first clock cycle.

公开(公告)号：EP1461712A2

公开(公告)日：2004-09-29

申请号：EP02795777.8

申请日：2002-12-06

Applicant: INTEL CORPORATION

Inventor： HARRIMAN, David ,  LEE, David ,  CRETA, Kenneth ,  AJANOVIC, Jasmin ,  SOLOMON, Gary

IPC: G06F13/40

CPC classification number: G06F13/4282 ,  G06F2213/0026

Abstract: A requesting device and a completer device are coupled via a high-speed serial interface within a computer system. The requesting device transmits a packet for a request transaction to a completer device. The completer device checks for error conditions in the course of servicing the request. If an error condition is found, the completer device transmits a completion packet with a completion status of something other than successful. The completion packet includes a completer identification field. The requesting device records the completer identification value and indicates in a register that a completion packet has been received with a non-successful completion status.

公开(公告)号：EP1141832A1

公开(公告)日：2001-10-10

申请号：EP99949955.1

申请日：1999-09-29

Applicant: INTEL CORPORATION

Inventor： HOLLAND, Kenneth ,  LEE, David ,  MEREDITH, Susan

IPC: G06F11/16 ,  G06F13/42

CPC classification number: G06F13/4213 ,  G06F11/1679

Abstract: A computer system (50) includes a bus (52), a first bus device (60), a core circuit (58) and a second circuit (54). The first bus device (60) is coupled to the bus (52) and adapted to furnish a first indication of data to a portion of a bus (52) beginning at a first clock cycle. The bus is capable of skewing the first indication to produce a second indication of the data at another portion of the bus (52) beginning at another clock cycle. The second circuit (54) is coupled to the bus (52) and is adapted to receive an indication of a selected latency time. The second circuit (54) is also adapted to transfer the data to the core circuit (58) in response to the second indication and regulate the transfer so that the circuit receives the data beginning at the selected latency time after the first clock cycle.