中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

16 records (took 0.028 seconds)

    DUAL POWER I/O RECEIVER
    1.
    发明申请
    DUAL POWER I/O RECEIVER 审中-公开

    公开(公告)号：WO2020068240A1

    公开(公告)日：2020-04-02

    申请号：PCT/US2019/040023

    申请日：2019-06-29

    Applicant: INTEL CORPORATION

    Inventor： MOSTOFA, Mohammed ,  CHENG, Roger K. ,  MARTIN, Aaron ,  MOZAK, Christopher ,  KAPPANGANTULA, Pavan Kumar ,  YANG, Hsien-Pao

    IPC: G11C11/4074 ,  G11C5/14

    Abstract: An apparatus is provided which comprises: a first circuitry to sample a first input signal to generate a first sampled signal, and to sample a second input signal to generate a second sampled signal, wherein the first input signal comprises data; a second circuitry to receive the first sampled signal and the second sampled signal, and to generate a first pair of differential signals; an offset cancellation circuitry to cancel or reduce an offset in the first pair of differential signals; and a latch to receive the first pair of differential signals subsequent to the cancellation or reduction of the offset, and to output a second pair of differential signals, wherein the second pair of differential signals is indicative of the data.

    DIFFERENTIAL CASCODE CURRENT MODE DRIVER
    3.
    发明申请
    DIFFERENTIAL CASCODE CURRENT MODE DRIVER 审中-公开
    差分电流模式驱动器

    公开(公告)号：WO2002084877A2

    公开(公告)日：2002-10-24

    申请号：PCT/US2002/009846

    申请日：2002-03-29

    Applicant: INTEL CORPORATION

    Inventor： MOONEY, Stephen ,  MARTIN, Aaron

    IPC: H03K19/0185

    CPC classification number: H04L25/0282 ,  H03K19/01721 ,  H03K19/018528 ,  H04L25/0272 ,  H04L25/0294

    Abstract: A current mode driver includes a tail current device, a differential pair of input transistors, cascode output transistors, and pre-charge circuits to charge cascode nodes between the differential pair of input transistors and the cascode output transistors. The current mode driver is driven by CMOS drivers that alternately turn the input transistors on and off. A wide-swing bias circuit provides bias voltages for the current mode driver. This bias voltage for the tail current device is closely matched to provide current matching between the bias circuit and the current mode driver.

    Abstract translation: 电流模式驱动器包括尾电流器件，差分输入晶体管对，共源共栅输出晶体管和预充电电路，用于对差分输入晶体管对和共源共栅输出晶体管之间的共源共栅节点进行充电。 电流模式驱动器由CMOS驱动器驱动，交替地将输入晶体管打开和关闭。 宽摆幅偏置电路为电流模式驱动器提供偏置电压。 尾电流器件的偏置电压紧密匹配，以提供偏置电路和电流模式驱动器之间的电流匹配。

    RECONFIGURABLE CLOCKING ARCHITECTURE
    5.
    发明申请
    RECONFIGURABLE CLOCKING ARCHITECTURE 审中-公开
    可重构时钟结构

    公开(公告)号：WO2017142664A1

    公开(公告)日：2017-08-24

    申请号：PCT/US2017/013799

    申请日：2017-01-17

    Applicant: INTEL CORPORATION

    Inventor： MANSURI, Mozhgan ,  MARTIN, Aaron ,  MCCALL, James A.

    IPC: G11C11/4076 ,  G11C7/22 ,  H03K3/03 ,  G05F1/575

    CPC classification number: G11C11/4076 ,  G06F1/10 ,  G06F13/4234 ,  G11C7/10 ,  G11C7/1087 ,  G11C7/222 ,  G11C11/4093 ,  H03K5/14 ,  H03K2005/00052 ,  H04L7/0337

    Abstract: Described is an apparatus which comprises: a comparator to be clocked by a clock signal to be provided by a clocking circuit, wherein the clocking circuit includes: a voltage controlled delay line having two or more delay cells; a multiplexer coupled to the voltage controlled delay line and operable to configure the clocking circuit as a ring oscillator with the voltage controlled delay line forming at least one delay section of the ring oscillator; and select logic coupled to the multiplexer, the select logic is to receive a signal indicating arrival of an input clock, and is to control the multiplexer according to the indication. Described is also an apparatus which comprises: a data path to receive input data; and a clock path to receive an input clock and to provide a preconditioned clock to the data path when the input clock is absent.

    Abstract translation: 描述了一种装置，包括：由时钟电路提供的时钟信号计时的比较器，其中时钟电路包括：具有两个或更多个延迟单元的电压控制延迟线; 多路复用器，其耦合到所述电压控制延迟线，并且可操作以将所述时钟电路配置为环形振荡器，所述电压控制延迟线形成所述环形振荡器的至少一个延迟部分; 并选择耦合到所述多路复用器的逻辑，所述选择逻辑将接收指示输入时钟到达的信号，并且根据所述指示来控制所述多路复用器。 还描述了一种装置，其包括：接收输入数据的数据路径; 和一个时钟路径，用于接收输入时钟，并在输入时钟不存在时为数据路径提供预处理时钟。

    CONTINUOUS-TIME EQUALIZER
    6.
    发明申请
    CONTINUOUS-TIME EQUALIZER 审中-公开
    连续均衡器

    公开(公告)号：WO2006116523A1

    公开(公告)日：2006-11-02

    申请号：PCT/US2006/015849

    申请日：2006-04-25

    Applicant: INTEL CORPORATION ,  MARTIN, Aaron ,  HANUOLU, Parvan ,  MOONEY, Randy

    Inventor： MARTIN, Aaron ,  HANUOLU, Parvan ,  MOONEY, Randy

    IPC: H03H11/04 ,  H04L27/01 ,  H04B3/14

    CPC classification number: H04L25/03878 ,  H04B3/145

    Abstract: A continuous-time equalizer includes a first transconductance circuit to set a gain of an amplified signal in a link and a second transconductance circuit to set a zero frequency in a transfer function of the equalizer. The zero frequency controls a frequency range of the signal amplified in the link based on the gain set by the first transconductance circuit.

    Abstract translation: 连续时间均衡器包括：第一跨导电路，用于设定链路中放大信号的增益;以及第二跨导电路，用于在均衡器的传递函数中设置零频率。 零频率基于由第一跨导电路设置的增益来控制在链路中放大的信号的频率范围。

    CONVERGED ADAPTIVE COMPENSATION SCHEME
    8.
    发明申请
    CONVERGED ADAPTIVE COMPENSATION SCHEME 审中-公开
    自适应补偿方案

    公开(公告)号：WO2016048506A1

    公开(公告)日：2016-03-31

    申请号：PCT/US2015/046227

    申请日：2015-08-21

    Applicant: INTEL CORPORATION

    Inventor： CHENG, Roger, K. ,  RUSU, Stefan ,  MARTIN, Aaron

    IPC: H04L12/701 ,  H04L12/951 ,  H04L25/02

    CPC classification number: G06F17/5063 ,  G06F2217/78 ,  H03M1/12 ,  H03M1/66

    Abstract: Described is an apparatus which comprises: logic to convert output of at least one sensor to a digital sensing signal; a router coupled to the sensor, the router to receive the digital sensing signal and to map into circuit data; and one or more communication interfaces, coupled to the router, to forward circuit data to a circuit endpoint. Described is a method which comprises: providing one or more digital sensing signals from a plurality of sensors; receiving the one or more digital sensing signals; generating packets of data using the one or more digital sensing signals; and providing the packets of data to one or more destinations.

    Abstract translation: 描述了一种装置，其包括：将至少一个传感器的输出转换为数字感测信号的逻辑; 路由器耦合到传感器，路由器接收数字感测信号并映射到电路数据中; 以及耦合到路由器的一个或多个通信接口，以将电路数据转发到电路端点。 描述了一种方法，其包括：从多个传感器提供一个或多个数字感测信号; 接收一个或多个数字感测信号; 使用所述一个或多个数字感测信号产生数据包; 并将数据包提供给一个或多个目的地。

    LOW SWING VOLTAGE MODE DRIVER
    9.
    发明申请
    LOW SWING VOLTAGE MODE DRIVER 审中-公开
    低电压电压模式驱动器

    公开(公告)号：WO2014105149A1

    公开(公告)日：2014-07-03

    申请号：PCT/US2013/046897

    申请日：2013-06-20

    Applicant: INTEL CORPORATION

    Inventor： MCCALL, James A. ,  BAINS, Kuljit S. ,  CONROW, Derek M. ,  MARTIN, Aaron

    IPC: G06F1/26

    CPC classification number: H03K19/0008 ,  G06F3/041 ,  G06F3/0412 ,  H03K19/0005 ,  H03K19/017509 ,  H03K19/017545

    Abstract: An output driver includes control logic configured to switch on a pull-up circuit and a pull-down circuit to provide an output impedance for a logic low on a transmission line. The output driver includes a variable pull-up resistor. The control logic is configured to switch on the pull-up circuit to a first value of impedance to drive a logic high on the transmission line. The control logic is configured to switch on the pull-up circuit to a second value of impedance and to switch on the pull-down circuit to provide the output impedance to drive a logic low on the transmission line. The system could alternatively be configured for the inverse to switch on a combination of pull-up and pull-down circuits for a logic high, where the pull-down circuit is switched on for a logic low.

    Abstract translation: 输出驱动器包括被配置为接通上拉电路和下拉电路以提供传输线路上的逻辑低电平的输出阻抗的控制逻辑。 输出驱动器包括一个可变上拉电阻。 控制逻辑被配置为将上拉电路接通到第一阻抗值，以驱动传输线上的逻辑高电平。 控制逻辑被配置为将上拉电路接通到第二阻抗值，并且接通下拉电路以提供输出阻抗以驱动传输线上的逻辑低电平。 可替代地，该系统可以被配置为反向以将逻辑高的上拉和下拉电路的组合打开，其中下拉电路被接通为逻辑低。

Patent Agency Ranking