公开(公告)号：WO2018118299A1

公开(公告)日：2018-06-28

申请号：PCT/US2017/062308

申请日：2017-11-17

Applicant: INTEL CORPORATION

Inventor： MODI, Mitul ,  RAORANE, Digvijay, A.

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/00

Abstract: A stacked-chip assembly including an IC chip or die that is electrically interconnected to another chip and/or a substrate by one or more traces that are coupled through sidewalls of the chip. Electrical traces extending over a sidewall of the chip may contact metal traces of one or more die interconnect levels that intersect the chip edge. Following chip fabrication, singulation may expose a metal trace that intersects the chip sidewall. Following singulation, a conductive sidewall interconnect trace formed over the chip sidewall is to couple the exposed trace to a top or bottom side of a chip or substrate. The sidewall interconnect trace may be further coupled to a ground, signal, or power rail. The sidewall interconnect trace may terminate with a bond pad to which another chip, substrate, or wire lead is bonded. The sidewall interconnect trace may terminate at another sidewall location on the same chip or another chip.

公开(公告)号：WO2017112328A1

公开(公告)日：2017-06-29

申请号：PCT/US2016/063733

申请日：2016-11-24

Applicant: INTEL CORPORATION

Inventor： DIAS, Rajendra ,  KUMAMOTO, Takashi ,  TOMITA, Yoshishiro ,  MODI, Mitul ,  HEPPNER, Joshua ,  LI, Eric

IPC: H01L23/552 ,  H01L21/56 ,  H05K9/00

CPC classification number: H01L23/552 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/3135 ,  H01L25/16 ,  H01L2224/73204

Abstract: Electromagnetically shielded electronic device technology is disclosed. In an example, a method of making an electronic device package can comprise providing a substrate having a conductor pad and an electronic component. The method can also comprise forming a conformal insulating layer on the substrate and electronic component. The conformal insulating layer conforms to the electronic component. The method can further comprise exposing the conductor pad. In addition, the method can comprise forming an electrically conductive electromagnetic interference (EMI) layer on the insulating layer and in contact with the conductor pad.

Abstract translation: 公开了电磁屏蔽电子设备技术。 在一个示例中，制造电子器件封装的方法可以包括提供具有导体焊盘和电子部件的衬底。 该方法还可以包括在衬底和电子部件上形成共形绝缘层。 共形绝缘层符合电子元件。 该方法可以进一步包括暴露导体焊盘。 此外，该方法可以包括在绝缘层上形成导电电磁干扰（EMI）层并与导电垫接触。

公开(公告)号：WO2018125050A1

公开(公告)日：2018-07-05

申请号：PCT/US2016/068722

申请日：2016-12-27

Applicant: INTEL CORPORATION

Inventor： MODI, Mitul ,  SANKMAN, Robert L. ,  MALLIK, Debendra ,  MAHAJAN, Ravindranath V. ,  ALUR, Amruthavalli P. ,  DENG, Yikang ,  LI, Eric J.

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/31

Abstract: An apparatus is provided which comprises: a plurality of dielectric layers forming a substrate, a plurality of first conductive contacts on a first surface of the substrate, a cavity in the first surface of the substrate defining a second surface parallel to the first surface, a plurality of second conductive contacts on the second surface of the substrate, one or more integrated circuit die(s) coupled with the second conductive contacts, and mold material at least partially covering the one or more integrated circuit die(s) and the first conductive contacts. Other embodiments are also disclosed and claimed.

公开(公告)号：WO2023038786A1

公开(公告)日：2023-03-16

申请号：PCT/US2022/041126

申请日：2022-08-22

Applicant: INTEL CORPORATION

Inventor： PIETAMBARAM, Srinivas V. ,  MARIN, Brandon C. ,  MALLIK, Debendra ,  IBRAHIM, Tarik A. ,  ECTON, Jeremy ,  KARHADE, Omkar G. ,  PENMECHA, Bharat Prasad ,  LI, Xiaoqian ,  DESHPANDE, Nitin A. ,  MODI, Mitul ,  NIE, Bai

IPC: H01L25/16 ,  G02B6/12 ,  H01L23/13 ,  H01L23/15 ,  H01L23/538 ,  H01L21/52

Abstract: An optoelectronic assembly is disclosed, comprising a substrate having a core comprised of glass, and a photonic integrated circuit (PIC) and an electronic IC (EIC) coupled to a first side of the substrate. The core comprises a waveguide with a first endpoint proximate to the first side and a second endpoint exposed on a second side of the substrate orthogonal to the first side. The first endpoint of the waveguide is on a third side of the core parallel to the first side of the substrate. The substrate further comprises an optical via aligned with the first endpoint, and the optical via extends between the first side and the third side. In various embodiments, the waveguide is of any shape that can be inscribed by a laser between the first endpoint and the second endpoint.

公开(公告)号：WO2019133008A1

公开(公告)日：2019-07-04

申请号：PCT/US2017/069138

申请日：2017-12-30

Applicant: INTEL CORPORATION ,  MALLIK, Debendra ,  SANKMAN, Robert L. ,  NICKERSON, Robert ,  MODI, Mitul ,  GANESAN, Sanka ,  SWAMINATHAN, Rajasekaran ,  KARHADE, Omkar ,  LIFF, Shawna M. ,  ALUR, Amruthavalli ,  CHAVALI, Sri Chaitra J.

Inventor： MALLIK, Debendra ,  SANKMAN, Robert L. ,  NICKERSON, Robert ,  MODI, Mitul ,  GANESAN, Sanka ,  SWAMINATHAN, Rajasekaran ,  KARHADE, Omkar ,  LIFF, Shawna M. ,  ALUR, Amruthavalli ,  CHAVALI, Sri Chaitra J.

IPC: H01L25/07 ,  H01L23/538 ,  H01L23/498 ,  H01L23/28 ,  H01L23/00

Abstract: Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra fine pitch (e.g., a pitch that is greater than or equal to 150 µm, etc.); (ii) a large die to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.

公开(公告)号：WO2017171859A1

公开(公告)日：2017-10-05

申请号：PCT/US2016/025659

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： HEPPNER, Joshua ,  MODI, Mitul

IPC: H01L23/552 ,  H01L23/48

Abstract: Semiconductor packages with electromagnetic interference (EMI) shielding structures and a method of manufacture therefor is disclosed. In some aspects, a shielding structure can serve as an enclosure formed by conductive material or by a mesh of such material that can be used to block electric fields emanating from one or more electronic components enclosed by the shielding structure at a global package level or local and/or compartment package level for semiconductor packages. In one embodiment, wire and/or ribbon bonding can be used to fabricate the shielding structure. For example, one or more wire and/or ribbon bonds can go from a connecting ground pad on one side of the package to a connecting ground pad on the other side of the package. This can be repeated multiple times at a pre-determined pitch necessary to meet the electrical requirements for shielding, e.g. less than or equal to approximately one half the wavelength of radiation generated by the electronic components being shielded.

Abstract translation: 公开了具有电磁干扰（EMI）屏蔽结构的半导体封装及其制造方法。 在一些方面，屏蔽结构可以用作由导电材料或通过这样的材料的网形成的外壳，该外壳可以用于阻挡从在全局封装级或本地封装的屏蔽结构封闭的一个或多个电子部件发出的电场 和/或用于半导体封装的隔室封装水平。 在一个实施例中，可以使用导线和/或带状结合来制造屏蔽结构。 例如，一个或多个导线和/或带状连接可以从封装一侧的连接接地焊盘走到封装另一侧的连接接地焊盘。 这可以以预定间距重复多次，以满足屏蔽的电气要求，例如， 小于或等于被屏蔽的电子元件产生的辐射波长的大约一半。

公开(公告)号：WO2017112327A1

公开(公告)日：2017-06-29

申请号：PCT/US2016/063731

申请日：2016-11-24

Applicant: INTEL CORPORATION

Inventor： LI, Eric ,  HEPPNER, Joshua ,  DIAS, Rajendra ,  MODI, Mitul

IPC: H01L23/552 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/60 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3185 ,  H01L23/552 ,  H01L24/97 ,  H01L2924/15159 ,  H01L2924/1815

Abstract: Electronic device package technology is disclosed. In one example, an electronic device package can include a bottom surface and a side surface extending from the bottom surface. The side surface can be oriented at a non- perpendicular angle relative to the bottom surface. In another example, an electronic device package can include a top planar surface having a first area, a bottom planar surface having a second area, and a side surface extending between the top surface and the bottom surface. The second area can be larger than the first area. In yet another example, an electronic device package can include a substrate defining a plane, an electronic component disposed on the substrate, and a layer of material disposed about a lateral side of the electronic component. The layer of material can be oriented at an angle of less than 90 degrees relative to the plane.

Abstract translation: 披露了电子器件封装技术。 在一个示例中，电子器件封装可以包括底部表面和从底部表面延伸的侧表面。 侧表面可以相对于底表面以非垂直角度定向。 在另一个示例中，电子器件封装可以包括具有第一区域的顶部平坦表面，具有第二区域的底部平坦表面以及在顶部表面和底部表面之间延伸的侧表面。 第二个区域可以比第一个区域大。 在又一个示例中，电子器件封装可以包括限定平面的衬底，设置在衬底上的电子部件以及设置在电子部件的横向侧周围的材料层。 材料层可以相对于平面以小于90度的角度取向。

公开(公告)号：EP4439664A2

公开(公告)日：2024-10-02

申请号：EP24188644.9

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： HEPPNER, Joshua ,  MODI, Mitul

IPC: H01L25/065

CPC classification number: H01L23/48 ,  H01L23/552 ,  H01L2224/9720130101 ,  H01L2924/1910720130101 ,  H01L2225/0653720130101 ,  H01L25/0655 ,  H01L2225/065120130101 ,  H01L2225/0650620130101 ,  H01L25/0657

Abstract: An example of a microelectronics package (500, 600), comprises a substrate (503) having a substrate surface, the substrate surface having an electronic component (510, 615) provided thereon and one or more ground pads (505, 507, 509) disposed on the substrate surface; and a shielding structure (520, 620) electrically connected to the one or more ground pads and mounted on the substrate surface and at least partially enclosing the electronic component, the shielding structure comprising a plurality of wires or a plurality of ribbons, wherein end portions of pairs of adjacent bond wires or ribbons of the shielding structure are connected to individual ground pads of the one or more ground pads and overlap one another in a circumferential direction around the electronic component.

公开(公告)号：EP4439664A3

公开(公告)日：2024-12-18

申请号：EP24188644.9

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： HEPPNER, Joshua ,  MODI, Mitul

IPC: H01L23/552 ,  H01L23/48 ,  H01L25/065

Abstract: An example of a microelectronics package (500, 600), comprises a substrate (503) having a substrate surface, the substrate surface having an electronic component (510, 615) provided thereon and one or more ground pads (505, 507, 509) disposed on the substrate surface; and a shielding structure (520, 620) electrically connected to the one or more ground pads and mounted on the substrate surface and at least partially enclosing the electronic component, the shielding structure comprising a plurality of wires or a plurality of ribbons, wherein end portions of pairs of adjacent bond wires or ribbons of the shielding structure are connected to individual ground pads of the one or more ground pads and overlap one another in a circumferential direction around the electronic component.