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    Die interconnect substrates, a semiconductor device and a method for forming a die interconnect substrate
    1.
    发明授权
    Die interconnect substrates, a semiconductor device and a method for forming a die interconnect substrate 有权

    公开(公告)号：US12224264B2

    公开(公告)日：2025-02-11

    申请号：US18385167

    申请日：2023-10-30

    Applicant: Intel Corporation

    Inventor： Rahul Jain ,  Ji Yong Park ,  Kyu Oh Lee

    IPC: H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

    Abstract: Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.

    Methods to pattern TFC and incorporation in the ODI architecture and in any build up layer of organic substrate
    5.
    发明授权
    Methods to pattern TFC and incorporation in the ODI architecture and in any build up layer of organic substrate 有权

    公开(公告)号：US11581271B2

    公开(公告)日：2023-02-14

    申请号：US16353164

    申请日：2019-03-14

    Applicant: Intel Corporation

    Inventor： Rahul Jain ,  Kyu-Oh Lee ,  Islam A. Salama ,  Amruthavalli P. Alur ,  Wei-Lun K. Jen ,  Yongki Min ,  Sheng C. Li

    IPC: H01L23/64 ,  H01L23/498 ,  H01L49/02 ,  H01L23/538

    Abstract: Embodiments include semiconductor packages. A semiconductor package includes a plurality of build-up layers and a plurality of conductive layers in the build-up layers. The conductive layers include a first conductive layer and a second conductive layer. The first conductive layer is over the second conductive layer and build-up layers, where a first via couples the first and second conductive layers. The semiconductor package also includes a thin film capacitor (TFC) in the build-up layers, where a second via couples the TFC to the first conductive layer, and the second via has a thickness less than a thickness of the first via. The first conductive layer may be first level interconnects. The build-up layers may be dielectrics. The TFC may include a first electrode, a second electrode, and a dielectric. The first electrode may be over the second electrode, and the dielectric may be between the first and second electrodes.

    Cavity structures in integrated circuit package supports
    6.
    发明授权
    Cavity structures in integrated circuit package supports 有权

    公开(公告)号：US11557489B2

    公开(公告)日：2023-01-17

    申请号：US16113109

    申请日：2018-08-27

    Applicant: Intel Corporation

    Inventor： Rahul Jain ,  Sai Vadlamani ,  Junnan Zhao ,  Ji Yong Park ,  Kyu Oh Lee ,  Cheng Xu

    IPC: H01L21/48 ,  H01L23/00 ,  H01L23/495 ,  H01L23/31

    Abstract: Disclosed herein are cavity structures in integrated circuit (IC) package supports, as well as related methods and apparatuses. For example, in some embodiments, an IC package support may include: a cavity in a dielectric material, wherein the cavity has a bottom and sidewalls; conductive contacts at the bottom of the cavity, wherein the conductive contacts include a first material; a first peripheral material outside the cavity, wherein the first peripheral material is at the sidewalls of the cavity and proximate to the bottom of the cavity, and the first peripheral material includes the first material; and a second peripheral material outside the cavity, wherein the second peripheral material is at the sidewalls of the cavity and on the first peripheral material, and the second peripheral material is different than the first peripheral material.

    Methods to incorporate thin film capacitor sheets (TFC-S) in the build-up films
    10.
    发明授权
    Methods to incorporate thin film capacitor sheets (TFC-S) in the build-up films 有权

    公开(公告)号：US11410921B2

    公开(公告)日：2022-08-09

    申请号：US16107920

    申请日：2018-08-21

    Applicant: Intel Corporation

    Inventor： Rahul Jain ,  Kyu Oh Lee

    IPC: H01L23/498 ,  H01G4/33 ,  H01L21/48 ,  H01G4/228

    Abstract: Embodiments disclosed herein include an electronics package and methods of forming such electronics packages. In an embodiment, the electronics package comprises a plurality of build-up layers. In an embodiment, the build-up layers comprise conductive traces and vias. In an embodiment, the electronics package further comprises a capacitor embedded in the plurality of build-up layers. In an embodiment, the capacitor comprises: a first electrode, a high-k dielectric layer over portions of the first electrode, and a second electrode over portions of the high-k dielectric layer.

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