公开(公告)号：WO2019133017A1

公开(公告)日：2019-07-04

申请号：PCT/US2017/069155

申请日：2017-12-30

Applicant: INTEL CORPORATION ,  STRONG, Veronica ,  ALEKSOV, Aleksandar ,  RAWLINGS, Brandon

Inventor： STRONG, Veronica ,  ALEKSOV, Aleksandar ,  RAWLINGS, Brandon

IPC: H01L25/065 ,  H01L25/07 ,  H01L23/498 ,  H01L23/538 ,  H01L23/485 ,  H01L23/00

Abstract: A device package and method of forming the device package are described. The device package includes a dielectric on a conductive pad, a first via on a top surface of conductive pad, where the first via extends through dielectric, and a conductive trace on dielectric. The device package has a second via on dielectric, where the conductive trace connects to first and second vias, and the second via connects to an edge of conductive trace opposite from first via. The device package may have a seed on dielectric, where the seed electrically couples to conductive trace, a first seed on the top surface of conductive pad, where the first via is on first seed, and a second seed on a top surface of first via, the second seed on surfaces of second via, where the conductive trace is on second seed disposed on both first and second vias.

公开(公告)号：WO2022265714A1

公开(公告)日：2022-12-22

申请号：PCT/US2022/022329

申请日：2022-03-29

Applicant: INTEL CORPORATION

Inventor： ALEKSOV, Aleksandar ,  KAMGAING, Telesphor ,  PRABHU GAUNKAR, Neelam ,  DOGIAMIS, Georgios C. ,  STRONG, Veronica

IPC: H01L23/498 ,  H01L23/492 ,  H01L23/15

Abstract: Embodiments disclosed herein include package substrates and methods of forming such package substrates. In an embodiment a package substrate comprises a core with a first surface and a second surface opposite from the first surface. In an embodiment, a buildup layer is over the first surface of the core. In an embodiment, a channel is through the core, where the channel extends in a direction that is substantially parallel to the first surface.

公开(公告)号：WO2022265708A1

公开(公告)日：2022-12-22

申请号：PCT/US2022/021728

申请日：2022-03-24

Applicant: INTEL CORPORATION

Inventor： ALEKSOV, Aleksandar ,  KAMGAING, Telesphor ,  STRONG, Veronica ,  DOGIAMIS, Georgios C. ,  PRABHU GAUNKAR, Neelam

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/15

Abstract: Embodiments disclosed herein include package substrates and methods of forming such package substrates. In an embodiment the package substrate comprises a core and buildup layers on the core. In an embodiment, first level interconnect (FLI) pads are on a topmost buildup layer, and the FLI pads have a pitch. In an embodiment, a plurality of vertically oriented planes are embedded in the core, and the vertically oriented planes are spaced at the pitch.

公开(公告)号：WO2019066815A1

公开(公告)日：2019-04-04

申请号：PCT/US2017/053793

申请日：2017-09-27

Applicant: INTEL CORPORATION

Inventor： STRONG, Veronica ,  ALEKSOV, Aleksandar

IPC: H01L23/13 ,  H01L23/00 ,  H01L25/07

Abstract: Techniques and mechanisms for providing an integrated resistive circuit element of a substrate which includes one or more organic dielectric layers. In an embodiment, the substrate includes dielectric layer portions, wherein conductors variously extend each in a respective one of the dielectric layer portions to a side region thereof. The resistive circuit element, integrated in or on the substrate, adjoins each of the dielectric layer portions. Seed layers are variously coupled each between a resistive material of the circuit element and a respective one of the conductors. An additional catalytic seed layer portion is disposed between the resistive material and at least one dielectric layer. In another embodiment, processing to form the resistive circuit element include an electroless deposition of the resistive material.

公开(公告)号：WO2022265712A1

公开(公告)日：2022-12-22

申请号：PCT/US2022/022179

申请日：2022-03-28

Applicant: INTEL CORPORATION

Inventor： ALEKSOV, Aleksandar ,  KAMGAING, Telesphor ,  STRONG, Veronica ,  PRABHU GAUNKAR, Neelam ,  DOGIAMIS, Georgios C.

IPC: G02B6/42

Abstract: Embodiments disclosed herein include electronic packages with a core that includes an optical waveguide and methods of forming such electronic packages. In an embodiment, a package substrate comprises a core, and a photonics die embedded in the core. In an embodiment, the electronic package further comprises an optical waveguide embedded in the core. In an embodiment, the optical waveguide optically couples the photonics die to an edge of the core.

公开(公告)号：WO2022265707A1

公开(公告)日：2022-12-22

申请号：PCT/US2022/021555

申请日：2022-03-23

Applicant: INTEL CORPORATION

Inventor： KAMGAING, Telesphor ,  STRONG, Veronica ,  PRABHU GAUNKAR, Neelam ,  DOGIAMIS, Georgios C. ,  ALEKSOV, Aleksandar ,  SWAN, Johanna M.

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/15 ,  H01L21/48

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to glass interposers or substrates that may be created using a glass etching process to enable highly integrated modules. Planar structures, which may be vertical planar structures, created within the glass interposer may be used to provide shielding for conductive vias in the glass interposer, to increase the signal density within the glass substrate and to reduce cross talk. Other embodiments may be described and/or claimed.

公开(公告)号：WO2019133016A1

公开(公告)日：2019-07-04

申请号：PCT/US2017/069154

申请日：2017-12-30

Applicant: INTEL CORPORATION ,  ALEKSOV, Aleksandar ,  STRONG, Veronica ,  RAWLINGS, Brandon

Inventor： ALEKSOV, Aleksandar ,  STRONG, Veronica ,  RAWLINGS, Brandon

IPC: H01L25/065 ,  H01L25/07 ,  H01L23/485 ,  H01L23/498 ,  H01L23/538

Abstract: A device package and a method of forming a device package are described. The device package includes a dielectric on a conductive pad, and a first via on a first seed on a top surface of the conductive pad. The device package further includes a conductive trace on the dielectric, and a second via on a second seed layer on the dielectric. The conductive trace connects to the first via and the second via, where the second via connects to an edge of the conductive trace opposite from the first via. The dielectric may include a photoimageable dielectric or a buildup film. The device package may also include a seed on the dielectric prior to the conductive trace on the dielectric, and a second dielectric on the dielectric, the conductive trace, and the first and second vias, where the second dielectric exposes a top surface of the second via.

公开(公告)号：WO2019133015A1

公开(公告)日：2019-07-04

申请号：PCT/US2017/069153

申请日：2017-12-30

Applicant: INTEL CORPORATION ,  STRONG, Veronica ,  ALEKSOV, Aleksandar ,  RAWLINGS, Brandon

Inventor： STRONG, Veronica ,  ALEKSOV, Aleksandar ,  RAWLINGS, Brandon

IPC: H01L25/065 ,  H01L25/07 ,  H01L23/485 ,  H01L23/00 ,  H01L23/498

Abstract: Device package and a method of forming a device package are described. The device package includes an interposer with interconnects on an interconnect package layer and a conductive layer on the interposer. The device package has dies on the conductive layer, where the package layer includes a zero-misalignment two-via stack (ZM2VS) and a dielectric. The ZM2VS directly coupled to the interconnect. The ZM2VS further includes the dielectric on a conductive pad, a first via on a first seed, and first seed on a top surface of the conductive pad, where the first via extends through dielectric. The ZM2VS also has a conductive trace on dielectric, and a second via on a second seed, the second seed is on the dielectric, where the conductive trace connects to first and second vias, where second via connects to an edge of conductive trace opposite from first via.

公开(公告)号：WO2019066977A1

公开(公告)日：2019-04-04

申请号：PCT/US2017/054638

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： ALEKSOV, Aleksandar ,  STRONG, Veronica ,  DARMAWIKARTA, Kristof ,  SARKAR, Arnab

IPC: H01L23/522 ,  H01L23/498

Abstract: A package substrate, comprising a package comprising a substrate, the substrate comprising a dielectric layer, a via extending to a top surface of the dielectric layer; and a bond pad stack having a central axis and extending laterally from the via over the first layer. The bond pad stack is structurally integral with the via, wherein the bond pad stack comprises a first layer comprising a first metal disposed on the top of the via and extends laterally from the top of the via over the top surface of the dielectric layer adjacent to the via. The first layer is bonded to the top of the via and the dielectric layer, and a second layer is disposed over the first layer. A third layer is disposed over the second layer. The second layer comprises a second metal and the third layer comprises a third metal. The second layer and the third layer are electrically coupled to the via.

公开(公告)号：EP4356424A1

公开(公告)日：2024-04-24

申请号：EP22825491.8

申请日：2022-03-29

Applicant: INTEL Corporation

Inventor： ALEKSOV, Aleksandar ,  KAMGAING, Telesphor ,  PRABHU GAUNKAR, Neelam ,  DOGIAMIS, Georgios C. ,  STRONG, Veronica

IPC: H01L23/498 ,  H01L23/492 ,  H01L23/15

CPC classification number: H01L23/13 ,  H01L23/473 ,  H01L23/3677 ,  H01L23/5384 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/15