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    HIGH PERFORMANCE, LOW COST MICROELECTRONIC CIRCUIT PACKAGE WITH INTERPOSER
    3.
    发明申请
    HIGH PERFORMANCE, LOW COST MICROELECTRONIC CIRCUIT PACKAGE WITH INTERPOSER 审中-公开
    高性能，低成本微电子电路封装带插座

    公开(公告)号：WO2002089207A2

    公开(公告)日：2002-11-07

    申请号：PCT/US2002/012088

    申请日：2002-04-19

    Applicant: INTEL CORPORATION

    Inventor： VANDENTOP, Gilroy ,  TANG, John ,  TOWLE, Steven

    IPC: H01L23/498

    CPC classification number: H01L23/49838 ,  H01L23/13 ,  H01L23/24 ,  H01L23/642 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/15173 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/19106 ,  H01L2924/3011 ,  Y10S257/924

    Abstract: A low cost packaging technique for microelectronic circuit chips fixes a die within an opening in a package core. At least one metallic build up layer is then formed on the die/core assembly and a grid array interposer unit is laminated to the build up layer. The grid array interposer unit can then be mounted within an external circuite using any of a plurality of mounting technologies (e.g., ball grid array (BGA), land grid array (LGA), pin grid array (PGA), surface mount technology (SMT), and/or others). In one embodiment, a single build up layer is formed on the die/core cassembly before lamination of the interposer.

    Abstract translation: 用于微电子电路芯片的低成本封装技术将芯片固定在封装芯的开口内。 然后在模具/芯组件上形成至少一个金属堆积层，并且将栅格阵列插入单元层叠到堆积层上。 然后可以使用多种安装技术（例如，球栅阵列（BGA），平面栅格阵列（LGA），针阵列阵列（PGA），表面贴装技术（SMT）等）中的任何一种将栅格阵列插入单元安装在外部环路内 ）和/或其他）。 在一个实施例中，在层压插入件之前，在芯/芯组件上形成单个堆积层。

    FORMING DEFECT PREVENTION TRENCHES IN DICING STREETS
    5.
    发明申请
    FORMING DEFECT PREVENTION TRENCHES IN DICING STREETS 审中-公开
    在临沂街道形成缺陷预防渠道

    公开(公告)号：WO2003046980A2

    公开(公告)日：2003-06-05

    申请号：PCT/US2002/036577

    申请日：2002-11-15

    Applicant: INTEL CORPORATION

    Inventor： MULLIGAN, Rose ,  HE, Jun ,  MARIEB, Thomas ,  MENEZES, Susanne ,  TOWLE, Steven

    IPC: H01L23/00

    CPC classification number: H01L21/304 ,  B23K26/40 ,  B23K2201/40 ,  B23K2203/50 ,  H01L21/78

    Abstract: A method of dicing a microelectronic device wafer comprising forming at least one trench in at least one dicing street on the microelectronic device wafer, wherein the trench prevents cracking and/or delamination problems in the interconnect layer of the microelectronic device wafers caused by a subsequent dicing by a wafer saw.

    Abstract translation: 一种切割微电子器件晶片的方法，包括在所述微电子器件晶片上的至少一个切割道中形成至少一个沟槽，其中所述沟槽防止所述微电子器件晶片的互连层中的裂缝和/或分层问题 微电子器件晶圆由随后由晶圆锯切割而产生。

    MICROELECTRONIC CIRCUIT PACKAGE HAVING DIE FIXED WITHIN A PACKAGE CORE
    6.
    发明申请
    MICROELECTRONIC CIRCUIT PACKAGE HAVING DIE FIXED WITHIN A PACKAGE CORE 审中-公开

    公开(公告)号：WO2003021674A3

    公开(公告)日：2003-03-13

    申请号：PCT/US2002/025089

    申请日：2002-08-06

    Applicant: INTEL CORPORATION (a Delaware Corporation)

    Inventor： DORY, Thomas ,  CUENDET, John ,  TANG, John ,  TOWLE, Steven ,  BRAUNISCH, Henning

    IPC: H01L23/495

    Abstract: A low cost microelectronic circuit package includes a single build up metallization layer above a microelectronic die. At least one die is fixed within a package core using, for example, an encapsulation material. A single metallization layer is then built up over the die/core assembly. The metallization layer includes a number of landing pads having a pitch that allows the microelectronic device to be directly mounted to an external circuit board. In one embodiment, the metallization layer includes a number of signal landing pads within a peripheral region kof the layer and at least one power landing pad and one ground landing pad toward a central region of the layer.

    CONNECTORIZATION PROCESS FOR OPTICAL CHIP-TO-CHIP INTERCONNECTS
    8.
    发明申请
    CONNECTORIZATION PROCESS FOR OPTICAL CHIP-TO-CHIP INTERCONNECTS 审中-公开
    光纤到芯片互连的连接过程

    公开(公告)号：WO2006039640A1

    公开(公告)日：2006-04-13

    申请号：PCT/US2005/035473

    申请日：2005-09-29

    Applicant: INTEL CORPORATION ,  TOWLE, Steven ,  LU, Daoqiang ,  BRAUNISCH, Henning

    Inventor： TOWLE, Steven ,  LU, Daoqiang ,  BRAUNISCH, Henning

    IPC: G02B6/30 ,  G02B6/36 ,  G02B6/42

    CPC classification number: G02B6/241 ,  G02B6/30

    Abstract: An optical package (100) comprising an optoelectric element (104) and a substrate (102) having a trench (214) therein, the trench (214) extending to an edge of the substrate (102), a waveguide array (114) positioned in the trench (214), the waveguide array (114) extending to the edge of the substrate (102), and a lid (216) attached or near the edge (116) of the substrate (102) and spanning a width of the waveguide array (114), the lid (116) including a recess (404) having a bottom (406), wherein the bottom (406) is in direct contact with a surface (704) of the waveguide array (114). The lid (116) and the substrate (102) form a connector (118) for optically connecting the optical package (100) to other components.

    Abstract translation: 一种包括光电元件（104）和其中具有沟槽（214）的衬底（102）的光学封装（100），所述沟槽（214）延伸到衬底（102）的边缘，波导阵列（114） 在所述沟槽（214）中，所述波导阵列（114）延伸到所述衬底（102）的边缘，以及盖（216），其附接或靠近所述衬底（102）的边缘（116）并跨越所述衬底 波导阵列（114），所述盖（116）包括具有底部（406）的凹部（404），其中所述底部（406）与所述波导阵列（114）的表面（704）直接接触。 盖（116）和基板（102）形成用于将光学封装（100）光学连接到其它部件的连接器（118）。

    ELECTROOPTIC ASSEMBLY
    9.
    发明申请
    ELECTROOPTIC ASSEMBLY 审中-公开

    公开(公告)号：WO2004029680A3

    公开(公告)日：2004-04-08

    申请号：PCT/US2003/028811

    申请日：2003-09-12

    Applicant: INTEL CORPORATION

    Inventor： TOWLE, Steven

    IPC: G02B6/42

    Abstract: An electrooptic assembly including a microelectronic package (20) and an optical substrate (62), wherein the optical substrate includes a coupler (70) and a waveguide (72). An electrooptic element (54) is disposed to convert an electrical signal from the microelectronic package (20) to an optical signal for transmission to the coupler (70) and waveguide (72), and/or to receive an optical signal and convert it to an electrical signal for transmission to the package (20).

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