公开(公告)号：WO2003054954A3

公开(公告)日：2003-07-03

申请号：PCT/US2002/038027

申请日：2002-11-26

Applicant: INTEL CORPORATION

Inventor： VANDENTOP, Gilroy ,  ZHENG, Jun-Fei

IPC: H01L21/60

Abstract: An electro-optic semiconductor package and fabrication method provides enhanced performance. An integrated circuit (IC) having one or more IC contact pads is provided, where the IC contact pads are connected to an IC on the IC wafer. An intermediate wafer having one or more intermediate contact pads is provided, where the intermediate contact pads are connected to an electro-optic arrangement on the intermediate wafer. The method further provides for direct copper bonding the IC contact pads to adjacent intermediate contact pads such that an electro-optic semiconductor package results.

公开(公告)号：WO2002089207A2

公开(公告)日：2002-11-07

申请号：PCT/US2002/012088

申请日：2002-04-19

Applicant: INTEL CORPORATION

Inventor： VANDENTOP, Gilroy ,  TANG, John ,  TOWLE, Steven

IPC: H01L23/498

CPC classification number: H01L23/49838 ,  H01L23/13 ,  H01L23/24 ,  H01L23/642 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/15173 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/19106 ,  H01L2924/3011 ,  Y10S257/924

Abstract: A low cost packaging technique for microelectronic circuit chips fixes a die within an opening in a package core. At least one metallic build up layer is then formed on the die/core assembly and a grid array interposer unit is laminated to the build up layer. The grid array interposer unit can then be mounted within an external circuite using any of a plurality of mounting technologies (e.g., ball grid array (BGA), land grid array (LGA), pin grid array (PGA), surface mount technology (SMT), and/or others). In one embodiment, a single build up layer is formed on the die/core cassembly before lamination of the interposer.

Abstract translation: 用于微电子电路芯片的低成本封装技术将芯片固定在封装芯的开口内。 然后在模具/芯组件上形成至少一个金属堆积层，并且将栅格阵列插入单元层叠到堆积层上。 然后可以使用多种安装技术（例如，球栅阵列（BGA），平面栅格阵列（LGA），针阵列阵列（PGA），表面贴装技术（SMT）等）中的任何一种将栅格阵列插入单元安装在外部环路内 ）和/或其他）。 在一个实施例中，在层压插入件之前，在芯/芯组件上形成单个堆积层。

公开(公告)号：WO2007041109A1

公开(公告)日：2007-04-12

申请号：PCT/US2006/037520

申请日：2006-09-26

Applicant: INTEL CORPORATION ,  HU, Chuan ,  LU, Daoquiang ,  VANDENTOP, Gilroy ,  RAMANATHAN, Shiriram ,  BASKARAN, Rajashree ,  DUBIN, Valery

Inventor： HU, Chuan ,  LU, Daoquiang ,  VANDENTOP, Gilroy ,  RAMANATHAN, Shiriram ,  BASKARAN, Rajashree ,  DUBIN, Valery

IPC: H01L23/367

CPC classification number: H01L24/83 ,  H01L21/4871 ,  H01L23/3735 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/18161 ,  H01L2924/19106 ,  H01L2924/00

Abstract: A method of fabricating a microelectronic package having a direct contact heat spreader, a package formed according to the method, a die-heat spreader combination formed according to the method, and a system incorporating the package. The method comprises metallizing a backside of a microelectronic die to form a heat spreader body directly contacting and fixed to the backside of the die thus yielding a die-heat spreader combination. The package includes the die-heat spreader combination and a substrate bonded to the die.

Abstract translation: 一种制造具有直接接触散热器的微电子封装的方法，根据该方法形成的封装，根据该方法形成的模具散热器组合以及包含该封装的系统。 该方法包括金属化微电子管芯的背面以形成直接接触并固定到管芯背面的散热器主体，从而产生模具散热器组合。 该封装包括模具散热器组合和与模具结合的衬底。

公开(公告)号：WO2005045927A1

公开(公告)日：2005-05-19

申请号：PCT/US2004/035892

申请日：2004-10-27

Applicant: INTEL CORPORATION (a Delaware Corporation) ,  VANDENTOP, Gilroy ,  MAHAJAN, Ravindranath ,  MYERS, Alan ,  MAVEETY, James ,  VU, Quat ,  LIST, Richard ,  KIM, Sarah ,  PRASHER, Ravi

Inventor： VANDENTOP, Gilroy ,  MAHAJAN, Ravindranath ,  MYERS, Alan ,  MAVEETY, James ,  VU, Quat ,  LIST, Richard ,  KIM, Sarah ,  PRASHER, Ravi

IPC: H01L23/473

CPC classification number: H01L23/473 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2224/82

Abstract: An integrated circuit to be cooled may be abutted in face-to-face abutment with a cooling integrated circuit. The cooling integrated circuit may include electroosmotic pumps to pump cooling fluid through the cooling integrated circuits via microchannels to thereby cool the heat generating integrated circuit. The electroosmotic pumps may be fluidically coupled to external radiators which extend upwardly away from a package including the integrated circuits. In particular, the external radiators may be mounted on tubes which extend the radiators away from the package.

Abstract translation: 要冷却的集成电路可以与冷却集成电路面对面邻接。 冷却集成电路可以包括电渗泵，以通过微通道将冷却流体泵送通过冷却集成电路，从而冷却发热集成电路。 电渗泵可以流体耦合到从包括集成电路的包装向上延伸的外部散热器。 特别地，外部散热器可以安装在使散热器远离封装的管上。

公开(公告)号：WO2003090278A3

公开(公告)日：2003-10-30

申请号：PCT/US2003/009681

申请日：2003-03-27

Applicant: INTEL CORPORATION

Inventor： VANDENTOP, Gilroy ,  CHIU, Chia-Pin ,  NAIR, Rajendran ,  LI, Yian-Liang

IPC: H01L23/367

Abstract: The present invention describes a method and apparatus for mounting a microelectronic device parallel to a substrate with an interposer and two heat sinks, one on each side of the substrate.

公开(公告)号：WO2002089207A3

公开(公告)日：2002-11-07

申请号：PCT/US2002/012088

申请日：2002-04-19

Applicant: INTEL CORPORATION

Inventor： VANDENTOP, Gilroy ,  TANG, John ,  TOWLE, Steven

IPC: H01L23/498

Abstract: A low cost packaging technique for microelectronic circuit chips fixes a die within an opening in a package core. At least one metallic build up layer is then formed on the die/core assembly and a grid array interposer unit is laminated to the build up layer. The grid array interposer unit can then be mounted within an external circuite using any of a plurality of mounting technologies (e.g., ball grid array (BGA), land grid array (LGA), pin grid array (PGA), surface mount technology (SMT), and/or others). In one embodiment, a single build up layer is formed on the die/core cassembly before lamination of the interposer.

公开(公告)号：WO2003090278A2

公开(公告)日：2003-10-30

申请号：PCT/US2003/009681

申请日：2003-03-27

Applicant: INTEL CORPORATION

Inventor： VANDENTOP, Gilroy ,  CHIU, Chia-Pin ,  NAIR, Rajendran ,  LI, Yian-Liang

IPC: H01L23/367

CPC classification number: H01L23/4006 ,  H01L23/13 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/4093 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2023/405 ,  H01L2023/4056 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/732 ,  H01L2224/73253 ,  H01L2924/01004 ,  H01L2924/01057 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1427 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/19042 ,  H05K1/0204 ,  H05K1/182 ,  H05K2201/09054 ,  H05K2201/10378 ,  H05K2201/10409 ,  H05K2201/10477 ,  H05K2201/10734 ,  H05K2203/1572

Abstract: The present invention describes a method and apparatus for mounting a microelectronic device parallel to a substrate with an interposer and two heat sinks, one on each side of the substrate.

Abstract translation: 本发明描述了一种用于利用中介层和两个散热片将平行于基板的微电子器件安装到基板的每一侧上的方法和设备。

公开(公告)号：WO2003054954A2

公开(公告)日：2003-07-03

申请号：PCT/US2002/038027

申请日：2002-11-26

Applicant: INTEL CORPORATION

Inventor： VANDENTOP, Gilroy ,  ZHENG, Jun-Fei

IPC: H01L21/60

CPC classification number: H01L24/81 ,  H01L27/156 ,  H01L31/0203 ,  H01L31/18 ,  H01L33/62 ,  H01L2224/80895 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00

Abstract: An electro-optic semiconductor package and fabrication method provides enhanced performance. An integrated circuit (IC) having one or more IC contact pads is provided, where the IC contact pads are connected to an IC on the IC wafer. An intermediate wafer having one or more intermediate contact pads is provided, where the intermediate contact pads are connected to an electro-optic arrangement on the intermediate wafer. The method further provides for direct copper bonding the IC contact pads to adjacent intermediate contact pads such that an electro-optic semiconductor package results.

Abstract translation: 电光半导体封装和制造方法提供增强的性能。 提供具有一个或多个IC接触焊盘的集成电路（IC），其中IC接触焊盘连接到IC晶片上的IC。 提供具有一个或多个中间接触焊盘的中间晶片，其中中间接触焊盘连接到中间晶片上的电光装置。 该方法进一步提供将IC接触焊盘直接铜接合到相邻的中间接触焊盘，从而导致电光半导体封装。

公开(公告)号：EP1497860A2

公开(公告)日：2005-01-19

申请号：EP03726148.4

申请日：2003-03-27

Applicant: INTEL CORPORATION

Inventor： VANDENTOP, Gilroy ,  CHIU, Chia-Pin ,  NAIR, Rajendran ,  LI, Yian-Liang

IPC: H01L23/367

CPC classification number: H01L23/4006 ,  H01L23/13 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/4093 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2023/405 ,  H01L2023/4056 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/732 ,  H01L2224/73253 ,  H01L2924/01004 ,  H01L2924/01057 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1427 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/19042 ,  H05K1/0204 ,  H05K1/182 ,  H05K2201/09054 ,  H05K2201/10378 ,  H05K2201/10409 ,  H05K2201/10477 ,  H05K2201/10734 ,  H05K2203/1572

Abstract: The present invention describes a method and apparatus for mounting a microelectronic device parallel to a substrate with an interposer and two heat sinks, one on each side of the substrate.

公开(公告)号：EP1456879A2

公开(公告)日：2004-09-15

申请号：EP02794048.5

申请日：2002-11-26

Applicant: Intel Corporation

Inventor： VANDENTOP, Gilroy ,  ZHENG, Jun-Fei

IPC: H01L21/60 ,  G02B6/42 ,  G02B6/43

CPC classification number: H01L24/81 ,  H01L27/156 ,  H01L31/0203 ,  H01L31/18 ,  H01L33/62 ,  H01L2224/80895 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00

Abstract: An electro-optic semiconductor package and fabrication method provides enhanced performance. An integrated circuit (IC) having one or more IC contact pads is provided, where the IC contact pads are connected to an IC on the IC wafer. An intermediate wafer having one or more intermediate contact pads is provided, where the intermediate contact pads are connected to an electro-optic arrangement on the intermediate wafer. The method further provides for direct copper bonding the IC contact pads to adjacent intermediate contact pads such that an electro-optic semiconductor package results.