公开(公告)号：US11664290B2

公开(公告)日：2023-05-30

申请号：US17459993

申请日：2021-08-27

Applicant: INTEL CORPORATION

Inventor： Rahul Jain ,  Kyu Oh Lee ,  Siddharth K. Alur ,  Wei-Lun K. Jen ,  Vipul V. Mehta ,  Ashish Dhall ,  Sri Chaitra J. Chavali ,  Rahul N. Manepalli ,  Amruthavalli P. Alur ,  Sai Vadlamani

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/532 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/3185 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/53295 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16227 ,  H01L2224/81 ,  H01L2224/83051 ,  H01L2924/18161

Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.

公开(公告)号：US20190103361A1

公开(公告)日：2019-04-04

申请号：US15721788

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Digvijay A. Raorane ,  Vipul V. Mehta

IPC: H01L23/538 ,  H01L23/12 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L21/563 ,  H01L23/12 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/498 ,  H01L23/5381 ,  H01L23/5384 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/83385 ,  H01L2224/92125 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2924/0665

Abstract: Electronic device package technology is disclosed. In one example, an electronic device package can include a substrate having a top surface and a vertical surface extending downward from the top surface. The top surface and the vertical surface can define an edge. The electronic device package can also include an electronic component disposed on the top surface of the substrate and electrically coupled to the substrate. In addition, the electronic device package can include an underfill material disposed at least partially between the electronic component and the top surface of the substrate. A lateral portion of the underfill material can extend from the electronic component to at least the edge. Associated systems and methods are also disclosed.

公开(公告)号：US11935805B2

公开(公告)日：2024-03-19

申请号：US18133868

申请日：2023-04-12

Applicant: Intel Corporation

Inventor： Rahul Jain ,  Kyu Oh Lee ,  Siddharth K. Alur ,  Wei-Lun K. Jen ,  Vipul V. Mehta ,  Ashish Dhall ,  Sri Chaitra J. Chavali ,  Rahul N. Manepalli ,  Amruthavalli P. Alur ,  Sai Vadlamani

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L23/532 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/3185 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/53295 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16227 ,  H01L2224/81 ,  H01L2224/83051 ,  H01L2924/18161

Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.

公开(公告)号：US11158558B2

公开(公告)日：2021-10-26

申请号：US16464547

申请日：2016-12-29

Applicant: INTEL CORPORATION

Inventor： Rahul Jain ,  Kyu Oh Lee ,  Siddharth K. Alur ,  Wei-Lun K. Jen ,  Vipul V. Mehta ,  Ashish Dhall ,  Sri Chaitra J. Chavali ,  Rahul N. Manepalli ,  Amruthavalli P. Alur ,  Sai Vadlamani

IPC: H01L23/48 ,  H01L21/00 ,  H01L21/44 ,  H05K7/00 ,  H01R9/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L23/532 ,  H01L23/498

Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.

公开(公告)号：US10403578B2

公开(公告)日：2019-09-03

申请号：US15721788

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Digvijay A. Raorane ,  Vipul V. Mehta

IPC: H01L23/12 ,  H01L23/053 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

Abstract: Electronic device package technology is disclosed. In one example, an electronic device package can include a substrate having a top surface and a vertical surface extending downward from the top surface. The top surface and the vertical surface can define an edge. The electronic device package can also include an electronic component disposed on the top surface of the substrate and electrically coupled to the substrate. In addition, the electronic device package can include an underfill material disposed at least partially between the electronic component and the top surface of the substrate. A lateral portion of the underfill material can extend from the electronic component to at least the edge. Associated systems and methods are also disclosed.

公开(公告)号：US20210391232A1

公开(公告)日：2021-12-16

申请号：US17459993

申请日：2021-08-27

Applicant: INTEL CORPORATION

Inventor： Rahul Jain ,  Kyu Oh Lee ,  Siddharth K. Alur ,  Wei-Lun K. Jen ,  Vipul V. Mehta ,  Ashish Dhall ,  Sri Chaitra J. Chavali ,  Rahul N. Manepalli ,  Amruthavalli P. Alur ,  Sai Vadlamani

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L23/532 ,  H01L23/498

Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.

公开(公告)号：US20210111088A1

公开(公告)日：2021-04-15

申请号：US16464547

申请日：2016-12-29

Applicant: INTEL CORPORATION

Inventor： Rahul Jain ,  Kyu Oh Lee ,  Siddharth K. Alur ,  Wei-Lun K. Jen ,  Vipul V. Mehta ,  Ashish Dhall ,  Sri Chaitra J. Chavali ,  Rahul N. Manepalli ,  Amruthavalli P. Alur ,  Sai Vadlamani

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.

公开(公告)号：US10373888B2

公开(公告)日：2019-08-06

申请号：US15395985

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Eric J. Li ,  Vipul V. Mehta ,  Digvijay A. Raorane

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

Abstract: An electronic package assembly is disclosed. A substrate can have an upper surface area. A first active die can have an upper surface area and a bottom surface, the bottom surface operably coupled to the substrate. A second active die can have an upper surface area and a bottom surface, the bottom surface operably coupled to the substrate. A capillary underfill material can at least partially encapsulate the bottom surface of the first active die and the second active die and extend upwardly upon inside side surfaces of the first and second active dies. A combined area of the upper surface area of the first active die and an upper surface area of the second active die is at least about 90% of the upper surface area of the substrate.

公开(公告)号：US20180190560A1

公开(公告)日：2018-07-05

申请号：US15395985

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Eric J. Li ,  Vipul V. Mehta ,  Digvijay A. Raorane

IPC: H01L23/31 ,  H01L25/065 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/3135 ,  H01L21/563 ,  H01L23/3121 ,  H01L23/3142 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0655 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2924/1304 ,  H01L2924/1815

Abstract: An electronic package assembly is disclosed. A substrate can have an upper surface area. A first active die can have an upper surface area and a bottom surface, the bottom surface operably coupled to the substrate. A second active die can have an upper surface area and a bottom surface, the bottom surface operably coupled to the substrate. A capillary underfill material can at least partially encapsulate the bottom surface of the first active die and the second active die and extend upwardly upon inside side surfaces of the first and second active dies. A combined area of the upper surface area of the first active die and an upper surface area of the second active die is at least about 90% of the upper surface area of the substrate.